M Tech Dissertations
Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3
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Item Open Access Front-end design for two lead ECG acquisition system(2020) Mohanta, Aditya; Mishra, BiswajitThe research presents a low power front-end design for electrocardiogram (ECG) acquisition system which is designed using 0.18mmCMOS technology with a supply voltage of 0.5V. The proposed architecture provides a fully digital solution to the traditional analog acquisition system. The design removes various analog block such as differential amplifiers, filters and passive elements such as switched capacitors. The design incorporates techniques such as time-domain amplification, moving average filtering and offset cancellation. The MA-VTC block performs the time-domain amplification and moving average filtering. The offset cancellation is provided by a negative feedback network. The system is designed to operate in sub-threshold region for low power consumption. The system provides output TDC signals corresponding to LEAD I and LEAD II signals of an ECG system.Item Open Access Physical design implementation of “ARP Block-4” module at 28nm “CHIPTOP” module at 90nm(Dhirubhai Ambani Institute of Information and Communication Technology, 2019) Sharma, Chinmay; Tatu, Aditya; Mehta, RahulVLSI design flow from RTL to GDSII consists of two phases, namely front-end design and back-end design. The physical design is the process of transforming a circuit description into the physical layout, which describes the position of cells and routes for the interconnections between them. Figure 1 shows a schematic representation of a layout. The main concern in the physical design of VLSI-chips is to find a layout with minimal area, further the total wire-length has to be minimized. For some critical nets there are hard limitations for the maximal wire-length. Due to its complexity, the physical design is normally broken in various sub-steps: 1) First the circuit has to be partitioned to generate some macro cells. 2) In the floorplanning phase the cells have to be placed on the layout surface. 3) After placement the global routing has to be done. In this step the `loose' routes for the interconnections between the single modules (macro cells) are determined. 4) In the detailed routing the exact routes for the interconnection wires in the channels between the macro cells have to be computed. 5) The last step in the physical design is the compaction of the layout, where it is compressed in all dimensions so that the total area is reduced. This classical approach of the physical design is strongly serial with many inter-dependencies between the sub-steps. For example during floorplanning and global routing there must be enough routing space reserved to complete the exact wiring in the detailed routing phase. Otherwise the placement has to be corrected and the global routing has to be computed again. In this project, back-end design (PnR) is done on two modules namely ChipTop at 90nm technology node and ARP Block4 at 28nm technology node. Physical Design is done with help of EDA tool Synopsys IC Compiler. EDA tools provide the design automations for IC design process which can reduce the design TAT. In order to reduce the design cost, the chip-area is reduced as small as possible. Reports at each stage of physical design are analysed. any congestion removal techniques are applied to remove congestion from ARP Block4 and improve timing.Item Open Access Design of 64-bit SRAM using single electron transistor(Dhirubhai Ambani Institute of Information and Communication Technology, 2016) Kale, Vishwamber N.; Parekh, RutuThe present day devices demand memory chips with larger size and smallphysical dimensions. This drives the designer to design high density memorydevices. The memory designed using CMOS technology do not have comparablespeed to match with the speed at which processor operate. Hence, we aretargeting to design high speed SRAM using Single Electron Transistor (SET). SETconsumes ultra low power. SET circuits can be stacked above the CMOS platform.The basic components of SRAM are decoder, sense amplifier, control block,write circuit driver and 6-T SRAM cell. To design stable SRAM, proper sizingof each transistor is reqiured. Decoder selects memory address for reading andwriting data. So proper designing of decoder is required. Due to high capcitanceof word line, Bitline doesnt get full voltage swing. Therefore, SRAM needs to bedesigned with higher stability. Selection of sense amplifier depends on the rateof bit-line discharging. To generate internal signals within SRAM for performingread and write operations designing a controller circuit is required.To achieve above mentioned specifications, stability of SRAM is verified usingN-Curve. Stability comparison is performed for both CMOS and SET basedSRAM. Dynamic decoders are used in SRAM, as they outperform conventionaldecoder in terms of power and delay. Comparison between SET and CMOS baseddecoder and sense amplifier is performed in terms of power and delay. Controllerdesign for generating internal signal for read and write operation is implementedfor both CMOS and SET based SRAM.We have verified the functionality of 64-bitSRAM by simulating read and write operations for SET and 45nm CMOS technology.Access time for SET based SRAM is 121 ps and for CMOS based SRAMis 872 ps. SET based SRAM takes total power as 723 nW and CMOS based takestotal power as 956 mW. In this work, we present SET based SRAM which is fasterand ultralow-power as compared to the 45nm CMOS based SRAM.Item Open Access Design and Analysis of Energy Neutral Wireless Sensor Nodes for Health and Environmental Monitoring Applications(Dhirubhai Ambani Institute of Information and Communication Technology, 2016) Pokhara, Ankur; Mishra, BiswajitThis thesis demonstrates investigation of an Energy Neutral System using EnergyHarvesters for Wireless Sensor Nodes (WSNs). For this purpose, we have implementedan Energy Harvesting system which consists of three parts: Energy Harvester(Solar cell), Power Management Unit (PMU) and a load (microcontrollerwith sensor and transmitter). A battery extender and a switching logic circuit forsensor node is developed to evaluate the efficiency of the proposed system. In thiswork we have implemented energy harvesting solutions for two different WSNs:for health and environmental monitoring applications. Health monitoring WSNis implemented to sense body temperature whereas Environmental monitoringWSN is used for sensing room temperature and humidity. Also the improvementin lifetime of coin cell for both the WSNs are calculated.A software algorithm has been developed to extend the proposed solar energyharvesting architecture for different applications and different WSNs. Furtherto this, an architecture for multiple energy harvesting has been proposed whichcan be used to connect multiple energy harvesters to the sensor node. Also anarchitecture for interfacing multiple sensors has been proposed. The architectureproposed in this work for introducing energy harvesting solutions to attain energyautonomy for multiple sensor WSN is implemented using commercially availableoff the shelf components.Item Open Access All-digital delay-line based ultra wide band transmitter architecture in 0.18m CMOS(Dhirubhai Ambani Institute of Information and Communication Technology, 2014) Patel, Chirag R.; Mishra, BiswajitUltra-Wide Band (UWB) technology has recently become a viable option for commercial wireless applications that require high data-rate and ultra low power demand. UWB technology operates between the frequency range of 3.1 GHz to 10.6 GHz and has to comply with Federal Communications Commission (FCC) standards with Power Spectral Density (PSD) below -41.3 dBm, that is also the lowest among all existing wireless systems. Thus it has a low communication range with high spatial resolution. Therefore, it finds applications in imaging and high precision positioning systems other than wireless sensor systems. Typically the UWB transmitters are implemented either using Orthogonal Frequency Division Multiplexing (OFDM) or base band techniques. Of all, the all digital technique finds interest within the research community due to the energy efficiency and benefits associated with current and future CMOS scaling. The proposed thesis discusses an all-digital UWB transmitter architecture based on all digital technique. It employs a delay line based architecture that works with Pulse Positioning Modulation (PPM), On Off Keying (OOK) and Delay Based Binary Phase Shift Keying (DB-BPSK) modulation schemes at two variable center frequencies (3.75GHz and 4.25GHz) with a fixed 500MHz bandwidth. The design also satisfies FCC indoor power spectral density requirements. We compare proposed design with the state of the art and conclude that it is comparable to existing designs and in certain cases better in view of the CMOS technology being used. The proposed design is implemented in 0.18mm technology based on a custom digital design employs OOK, PPM and DBBPSK Modulation Schemes. The Pulse Repetition Frequency (PRF) can be 100M, with 2 center frequencies (3.75GHz and 4.25GHz) with output amplitude of 120mV and achieves Energy/pulse at 16.59 pJ/p.Item Open Access Design of a novel high linearity down conversion mixer for GSM band applications(Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Srinaga, Nikhil N.; Gupta, SanjeevDouble balanced Gilbert cell mixer (GCM) is the mostly used kind of mixer as it provides conversion gain and has port to port isolation. This mixer lacks in linearity and noise figure which are to be taken care in designing mixer. Linearity is important for mixer design, to get an undistorted signal at its output. Similarly noise figure of double balanced GCM is more due to more number of components and is to be decreased to add less noise to RF signal. To increase the linearity of mixer, necessary changes are to be done at transconductance stage. The linearity of the mixer proposed is increased, by making use of an additional capacitor in parallel to gate capacitance and derivative superposition method. Derivative superposition method needs more number of transistors at transconductance stage resulting in increase of parasitic capacitance, resulting in an increase of flicker noise from indirect mechanism. This flicker noise due to parasitic capacitance is reduced by placing a tuned inductor in parallel to itItem Open Access CMOS current-based mixed-signal architecture for vector-matrix multiplication(Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Chhaya, Vaibhav; Zaveri, Mazad SIn present days electronic devices become faster. Computations like vector matrix multiplication become more and more compliant and lengthy. For that CMOS based vectormatrix multiplication architecture, with external digital interface and internal current-based analog operation is presented here. The basic circuits within this architecture are: a binary multiplier that contains a static memory, a current source, a current accumulator and current-to-voltage convertor. The external operand arrives sequentially, so a serial-to-parallel shift-register memory is also implemented. In LTSpice, using 180nm CMOS technology, I have implemented a vector-matrix multiplier circuit that simultaneously performs 64×4 binary multiplications.Item Open Access Auto tuning circuit for continuous time filters(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Nadimenti, Rakesh; Sen, SubhajitThis thesis presents the design of auto tuning circuit for continuous time filters and is designed for applications that require high linearity and moderate precision. This scheme is used to improve tuning range of 50% and obtain an accuracy of 2-7 %. We use discrete capacitor bank to tune RC time constant instead of varying the g m (Tran conductance) to preserve linearity. The auto tuning circuit consists of analog integrator, voltage comparator, capacitor bank, clock generator and a digital tuning engine. By using tuning logic we can generate a control word and set ON chip integrator capacitor to obtain desired RC time constant. The discrete capacitor tuning scheme is designed in 180nm technology to study about the performance of tuning circuit and is simulated in Cadence design environment.Item Open Access CMOS RFIC mixer design(Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Gupta, Mukesh; Gupta, SanjeevA CMOS RF (Radio Frequency) up/down conversion mixer results in a reasonable increase in transceiver integration and a reduction in cost. The design of mixers faces many compromises between conversion gain(GC), local oscillator (LO) power, linearity, noise figure (NF), port-to-port isolation, voltage scaling and power consumption. Mixer linearity is a very important parameter in transceiver design, because system linearity is often limited by the first down-conversion mixer due to a relatively large signal compared with that at the LNA input. Since active FET (Field Effect Transistor) mixers achieve conversion gain with lower LO power than their passive counterparts, the active CMOS single-balanced and double-balanced Gilbert mixers are commonly used in the CMOS transceiver design. Compared with the single-balanced counterpart, the double balanced mixer has better port-to- port isolation due to symmetrical architecture. The double-balanced mixer has a higher noise figure due to more noise generators. The overall Gilbert mixer linearity is controlled primarily by the transconductance stage if the LO-driven transistors act as good switches. This report describes a Gilbert cell mixer with source degeneration for 900 MHz frequency. The circuit converts a 900 MHz RF signal directly to base band [IF (Intermediate frequency) 45 MHz] using an 855 MHz LO frequency. The mixer uses common source MOSFETs with inductive degeneration to convert the input RF voltage to a current. This current is then steered using a switching network composed of MOSFETs that is driven with the LO and a 180 degree phase-shifted version of the LO. Gilbert Mixer achieves gain through an active predriver [The V-I (voltage to current) converter]. This V-I converter is highly nonlinear; hence, the Gilbert Mixer distortion performance is worse. This thesis tries to propose a simple linearity improvement technique for Gilbert Cell Mixer by including an additional capacitor located in parallel with the intrinsic gate-source capacitor of the common source transconductance stage. Also, to reduce the flicker noise of the switching transistors which depends on the frequency and circuit capacitance at the common source node of the switching stage, a method is used to reduce this capacitance by adding an extra inductor that helps for simultaneously match low 1/f noise, high linearity and low NF at the expense of Conversion gain. The design is based upon the third order intermodulation distortion (IM3) and output current equations of MOSFETs and flicker noise equation when it is subjected to an ac input signal. The performance has been verified using Agilent’ Advanced Design System (ADS) simulations. The designed mixer has a voltage conversion gain of 15.804 dB, NFSSB of 6.565 dB, NFDSB=3.975 dB, IIP3 of -1.158 dBm, OIP3 USB of 14.699 dBm, OIP3 LSB of 14.646 dBm, LO to IF isolation of -27.532 dB, LO to RF isolation of -69.365 dB and RF to IF isolation of -56.554 dB for single ended RF Input.Item Open Access CMOS latched comparator design for analog to digital converters(Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Gupta, Amit Kumar; Parikh, Chetan D.Conventional comparators are at the two extremes as far as power delay product and isolation between input and output is concern. Either they achieved very good isolation at the cost of power in the preamplifier or save the static power dissipation in preamplifier in the latching mode which increases the feed through. In this thesis work we propose an optimized CMOS Latch Comparator. The simulation result based on .18um technology, shows the working of the comparator at 500 MHz, with moderate power delay product and isolation compared with the conventional architecture.