M Tech Dissertations

Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3

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20102

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Subject: search.filters.subject.CMOS Comparators

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    Design of the high speed, high accuracy and low power current comparators
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Chasta, Neeraj Kumar; Parikh, Chetan D.
    Comparators are non linear, decision making analog circuits, which find wide spread application in data converters, data transmission and others. Comparison can be done in terms of “Voltage” or “Current”. A current comparator can be referred as trans-impedance amplifiers which compares applied input currents and generate CMOS compatible output voltage. In this work, study and simulations of various current domain comparator circuits have been done; some of these follow basic analog circuit concepts like current mirroring and Voltage current feedback. This thesis presents a novel idea for analog current comparison with controlled hysteresis. Proposed circuit is based on current mirror and latching techniques. Comparator presented is designed optimally in 0.18μm CMOS process in LTspice environment. Designing issues have also been discussed for no hysteresis (or very less hysteresis) case, where comparator gives higher accuracy and speed at the cost of increased power consumption. In addition to this a simple circuit is proposed which satisfies high speed, high accuracy and low power consumption constraints for the mentioned technology parameters. It utilizes amplification properties of Common gate circuit for generating CMOS compatible output voltage by comparison of applied input signal current and reference current
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    ItemOpen Access
    High speed, low offset voltage cmos comparator
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Sheikh, Parveen; Parikh, Chetan D.
    The Analog to digital converters are the key interface blocks between the continuous time domain and the discrete-time digital domain. The performance of high-speed data conversion and digital communication interfaces is generally limited by the speed and precision with which the function of comparison can be performed. Thus, comparator speed and precision play a vital role in high performance ADC’s. CMOS comparators suitable for integration in VLSI technologies have been successfully realized for audio frequency applications, such as analog - to-digital (A/D) converters. The speed and resolution of MOSFET comparators are typically limited by the inherent MOSFET characteristics of low trans-conductance and relatively large device mismatches. However, there are several techniques for dynamic offset cancellation, dynamic biasing, and analog pipelining which significantly improve the speed and resolution achievable in an MOS based comparator. The thesis proposes a novel approach which minimizes the offset of pre-amplifier as well as the latch with increment in the speed of the comparator. The total offset thus referred back to the input is minimized and hence the pre-amplifier gain be relaxed. The CMOS circuit is implemented in 0.18 μm technology and simulated in LT-Spice.