M Tech Dissertations
Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3
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Item Open Access Design and analysis of ultra wideband low noise amplifier(Dhirubhai Ambani Institute of Information and Communication Technology, 2018) Dhami, Aarushi; Gupta, SanjeevWith the advent of wireless technology, ultra wide band systems due to their fast data rate transmission have gained momentum. One of the basic building blocks of the receiver - Low Noise Amplifier (LNA) has seen various design transformations. Initially, low noise amplifiers were designed for narrowband applications. However, their operation was limited. With more applications of wireless technology increasing day by day, there is a need to develop systems that can handle wide frequency ranges. Designing low noise amplifier for wideband application is a challenging task. The main objective is to achieve as low noise figure as possible and maintain a constant gain over the frequencies of interest. First and foremost task is to decide on the transistor technology to be employed. With the various technologies available, MOSFET is chosen for this work due to its various benefits and simplicity in the structure. In this work, a LNA has been first designed for a single frequency, 2.4 GHz. The work is then extended for 3-5 GHz range. A 2 stage amplifier is implemented with a reactive input matching network. The first stage is a cascode stage with the source of first MOSFET degenerated using an inductor. This is followed by a single CS stage which is also responsible for wideband output matching. The work then proceeds to the designing of amplifier for 3-10 GHz range. The implemented design is a 3 stage amplifier. The topology uses the concept of mutual inductance between the inductors. All the circuits are designed and simulated in Advanced Design System (ADS). Also, the technology used here is 0.18mm CMOS.Item Open Access Low-power pipelined crypto-core using a backup flip-flop(Dhirubhai Ambani Institute of Information and Communication Technology, 2015) Patel, Sagar; Bhatt, AmitWith increasing clock frequencies, power-aware computing has become a critical concern in the VLSI design. One of the most effective and widely used method for lowering the power is DVS (Dynamic Voltage Scaling), which is the basic idea behind making low-power pipeline. Total power consumed by the system consists of dynamic power and leakage power. They both depend on the supply voltage, as they decrease with a decrement in supply voltage. But lower supply voltage causes more delays at the gate level, as there is less amount of voltage to charge the output capacitance of a gate. These delays can cause timing violations in the critical path. So, if the supply voltage of the system could be reduced somehow without affecting the overall functionality of the system, great power saving can be achieved. Usual DVS techniques need to have margin for process and temperature variations or any local variations. These voltage margins make the design less efficient in terms of power. Backup flip-flop can be used for the critical path, which operates on the different clock, delayed by some specific amount of delay. It covers the effect of voltage reduction as well as process and temperature variations with all local variation effects, which can affect delay in any manner. If there is any error, it needs to be corrected for a correct functionality of the system. Error correction mechanism and the architectural overview of AES crypto-core is also discussed, as it is the chosen design on which this concept would be implemented. Similar concept has been successfully tried out on Alpha processor with satisfactory result. All the simulations shown are post-synthesis or post-route simulations so that they reflect the approximated delays and timing checks of logical gates and interconnects. Simulations and synthesis were performed using Cadence NC-Launch and Encounter RTL Compiler respectively. ’Nangate Opencell Library’ with 45nm technology was used for the synthesis.Item Open Access Path planning of data mule using responsible short circuit with steiner points(Dhirubhai Ambani Institute of Information and Communication Technology, 2015) Vora, Ankitkumar; Srivastava, Sanjay; Sunitha, V.We have studied the problem of data aggregation method in wireless sensor network using the data mule. In data mule approach, Data mule is the mobile entity which can collect the data from stationary sensor node in the network. Data mule approach significantly improves the network lifetime. Network lifetime is main concern while designing the application of sensor network because most of the time sensor nodes die due to power discharge. On the other hand Data mule approach increases the data latency compared to other existing methods. There is a trade-off between network lifetime and data latency. Data latency of the data mule can be minimized using the proper motion planning of the data mule. As part of the motion planning we have studied the path selection problem for data mule using the Responsible short circuit algorithm. Responsible short circuit algorithm finds the equivalent responsible edge for two or more consecutive edges of that path. Using the Steiner node placement at the overlap region of sensor node’s communication can further improve the path for the data mule. We have combined the Responsible short circuit algorithm with Steiner node placement and tested using the simulation on java technology. This combination significantly improves the path length compared to existing approaches. We have tested the Responsible short circuit without Steiner node algorithm and Responsible short circuit with Steiner node algorithm for Uniform node deployment as well as the Cluster node deployment. We also have thought about the hybrid approach of Clustering and data mule approach which can improve the path selected for data mule.Item Open Access D-latch based low power memory design(Dhirubhai Ambani Institute of Information and Communication Technology, 2015) Tripathi, Saurabh; Mishra, BiswajitLow power consumption is the main attraction of the digital circuit design in the Sub threshold region of operation. In this region of operation less energy is consumed for active operation and less leakage power is dissipated than higher voltage alternatives. As a trade-off circuits operate slowly because the supply voltage is less than the threshold voltage of the transistors. Sub-threshold operation is considered as an effective solution in designs where low power consumption is the prime concern and operating speed can be sacrificed. The sub-threshold systems need the same voltage level operated memory design. Also, the sub-threshold memory design must be robust in terms of SNM (signal to noise margin) as the operating supply voltage is few hundreds of millivolts depending on technology node. This demands the architecture that ensures the effective data read/write operation under all critical conditions. This research work mainly focuses on D-Latch based 128 Byte full custom memory array and memory controller design. Starting with different latch architectures’ minimum operating supply voltage comparison, the complete Byte addressable memory design flow including row/column decoder design, memory controller design has been discussed. The complete layout of the memory, performance results under an application and its different parameters have also been included in the report. All the design parameters and the simulation results are produced for 0.18μm process.Item Open Access Single electron transistor based 4-bit ALU design, simulation and optimization(Dhirubhai Ambani Institute of Information and Communication Technology, 2015) Joshi, Rathin K.; Parekh, RutuObjective of this thesis work is to create and optimize Single Electron Transistor(SET) based digital design. In present era for electronics, alternative approaches, other than CMOS (like SET,finFET,quantom dot) are much required. This is because of down scaling in MOSFET does not provide efficient results, mainly less than 10 nm feature size. In order to exhibit its applications, SET based digital design of 4-bit multifunctional ALU has been compared with 45 nm CMOS technology. Further using, circuit architecture optimization is performed, which results in significant improvement in design. Entire analysis is done in hierarchical manner: First gate level implementation and its comparison is done, followed by modular performance comparison and finally 4-bit ALU design is compared. So far, no one has done such analysis for design like SET based multifunctional computational tool. Finally, we can conclude that proposed design is energy efficient than 45 nm CMOS or hybrid SET CMOS design. In terms of PDP, SET based optimized design results in 93 % improvment than existing 45 nm CMOS. Transient analysis and PDP analysis have been done in bottom up approach. Low drivabilty and room temeprature operability were the two bottlenecks in SET based design. In this thesis work, design parameters are taken which are appropriate for room temparature, Drivability of SET in increased by modifying circuit architecture. With research advnacement, these two drawbacks have been overcome. In addition to these advantages, all the fabrication parameters are in practically feasible. Hence, proposed design can be fabricated and work at room temprature. SET’s multivalued application has also been verified by considering an example of Qunatizer. Aim behind selecting quantizer is because it is the most basic unit for SET based ADC & DAC circuits. By using only 2 SETs, quantizer is implemented, which is generally bulkier circuit in case of CMOS. This kind of ”Unlike CMOS applications” have few novel benefits with better performance.Item Open Access Design of CMOS front end for 900MHz RF receiver(Dhirubhai Ambani Institute of Information and Communication Technology, 2004) Harshey, Jitendra Prabhakar; Bhatt, AmitPortable wireless personal communication systems such as cellular phones, message pagers, and wireless modems traditionally have been built from a mixture of IC technologies. In fact if we section a commercial cellular phone, we could find many separate ICs together linked in the analog section. Moreover some of these ICs are realized on GaAs substrate, others on bipolar Silicon and only the digital section is integrated on CMOS substrate. One of the main challenges facing complete integration of receiver (transmitter) hardware has been a lack of suitable on-chip RF and IF filtering. This approach increases system complexity, cost, and power consumption. The aim of this thesis consists in the investigating the characteristic of RF building blocks that constitute an integrated RF receiver. This thesis, is the balance between microelectronic and microwave, and investigates the bottlenecks in the fully integration of an RF receiver, and is particularly focused on the design of high quality passive devices and high performance low noise amplifiers. This receiver is part of a single chip transceiver, which operates in the 902-928 MHz ISM band. The receiver combines a balanced low-noise amplifier; down conversion mixers, low pass channel-select filters, and IF amplifiers all in one single CMOS IC. Noise components of MOS at high frequencies were studied in detail. Device properties unique to CMOS are exploited to obtain highly linear RF circuits. In design of low noise amplifier, I concentrated my efforts on minimizing the value of passive devices so that all of them can be fabricated on single chip. For this I undertook several optimizations and tradeoffs. Particularly the noise power trade-off with inductors value was stressed on. LNA had three primary design specifications of input impedance matching, gain and noise. I also experimented on several techniques of input match. The results obtained are suited to the needs fairly well. In the mixer design, my primary goal was to design a doubly balanced mixer for single ended inputs. This was necessitated because the antenna signal received was single ended before the LNA and even in LNA, due to several considerations; I obtained a single ended output. Finally this report contains all my designs and simulation results.