M Tech Dissertations

Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3

Browse

Subject: search.filters.subject.Complementary

Search Results

Now showing 1 - 5 of 5
  • Thumbnail Image
    ItemOpen Access
    High speed, low offset voltage cmos comparator
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Sheikh, Parveen; Parikh, Chetan D.
    The Analog to digital converters are the key interface blocks between the continuous time domain and the discrete-time digital domain. The performance of high-speed data conversion and digital communication interfaces is generally limited by the speed and precision with which the function of comparison can be performed. Thus, comparator speed and precision play a vital role in high performance ADC’s. CMOS comparators suitable for integration in VLSI technologies have been successfully realized for audio frequency applications, such as analog - to-digital (A/D) converters. The speed and resolution of MOSFET comparators are typically limited by the inherent MOSFET characteristics of low trans-conductance and relatively large device mismatches. However, there are several techniques for dynamic offset cancellation, dynamic biasing, and analog pipelining which significantly improve the speed and resolution achievable in an MOS based comparator. The thesis proposes a novel approach which minimizes the offset of pre-amplifier as well as the latch with increment in the speed of the comparator. The total offset thus referred back to the input is minimized and hence the pre-amplifier gain be relaxed. The CMOS circuit is implemented in 0.18 μm technology and simulated in LT-Spice.
  • Thumbnail Image
    ItemOpen Access
    Design of CMOS voltage controlled oscillator for high tuning range
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Nayudu, Bharath Kumar; Gupta, Sanjeev
    The main objective of the work is to design a CMOS voltage controlled oscillator for higher tuning range. Today there is a great need for multi-standard wireless receivers in the wireless communications. A receiver is to be designed such that it receives data from the different frequency bands and standards. It is essential to design an oscillator to adhere to some of the standards like CDMA, GSM, GPRS and others. CMOS was the ideal choice for this work because of its low power consumption compared to other technologies and its immunity to the noise. In the design of the tank circuit, binary weighted capacitive array technique (BWCA), discrete variable inductor by using MOS switch and variable capacitor for continuous tuning have been used. By using all the above three techniques, a higher tuning range has been achieved.
  • Thumbnail Image
    ItemOpen Access
    Implementation of constant gm CMOS op-amp input stage using overlapping of transition region at 0.18 um technology
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Singh, Ram Sahay; Parikh, Chetan D.
    Operational amplifier is the backbone of most of analog circuit design. For low voltage applications, op-amp should have a rail-to-rail common mode input voltage. This report describes the implementation of a constant gm rail-to-rail CMOS op-amp using complementary input pairs, at 0.18µm MOS technology. The concept used to make the input transconductance (gm) constant is the overlapping of transition regions of n-pair and p-pair tail transistors using a DC level shifter [2]. A constant gm input stage insures a uniform frequency response for the entire common mode input range. It also improves the Common Mode Rejection Ratio (CMRR). The results of the designed op-amp show that it has a rail-to-rail input common mode range and a rail-to-rail output voltage swing. For rail-to-rail output voltage swing a Class AB output stage is used. Layout of the chosen architecture is made using 0.18µm technology. Comparisons of pre-layout and post-layout simulation results are done.
  • Thumbnail Image
    ItemOpen Access
    Receiver amplifier design using CMOS current feedback amplifier and current conveyors
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Kaushik, Gaurav; Nagchoudhuri, Dipankar
    In the world of high-speed communications, systems involving high-speed data transfer require circuits with innovative features for good performance in terms of speed and power consumption. These data transfer systems constitute of large number of data channels each constituting of driver unit, transmission lines and a receiver unit. The receiver unit has small differential signals as the input. The designed receiver amplifier is required to have wide bandwidth, large slew rate and at the same time, capability to convert the differential input signal to single ended amplified signal without much distortion. For large number of data channels, it is also required that the power consumption of the receiver unit is minimal. In this work, a model for the receiver amplifier design is implemented using a closed loop amplifier and a differential to single ended converter. Current feedback amplifier is selected for the design of the closed loop amplifier due to their advantages over other topologies in high-speed design. Current feedback amplifiers have current on demand architecture that provides them dynamic current from the supply rails for charging or discharging load for large input signals. The differential to single ended converter is designed using two translinear positive second generation current conveyors. Translinear current conveyors due to their simple circuitry and dynamic current supply during large input signals are able to provide large bandwidth and low loss of signal resulting in very high-speed signal processing. The amplifier model is implemented in MOSIS 0.5 µm single-well technology using BSIM 3.0 model parameters. The obtained results are discussed in the end along with comments on the performance of the current mode circuits involved – current feedback amplifier and current conveyor.
  • Thumbnail Image
    ItemOpen Access
    Low power high slew-rate adaptive biasing circuit for CMOS amplifiers
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Rao, A. Narayana; Parikh, Chetan D.
    Adaptive biasing technique in analog and mixed signal integrated circuit design is used mainly to reduce the power and improve the driving capability. It has found many applications, like power amplifiers in RF communication systems whose biasing current is adjusted based on the detected input RF signal level. In RF tuning circuits filters can be automatically tuned simply by varying the bias current of the transconductance amplifier with respect to the control voltage. Existing techniques uses different methods like dynamically switching the current, using feed back, etc. Some of these are area efficient techniques and some are power efficient techniques. In this work, a new adaptive biasing scheme is proposed which shows excellent results in terms of both area and power without affecting amplifier design. It uses a simple input pair to sense input signals, current mirrors to generate a difference between two currents, this difference in current varies linearly with the input signal while nonlinearity is cancelled out. Simulation results shows about 80% of quiescent power can be saved while maintaining the amplifier small signal characteristics.