M Tech Dissertations

Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3

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Subject: search.filters.subject.Complementary metal oxide semiconductor

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Now showing 1 - 6 of 6
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    Design and Performance Benchmarking of Hybrid FinFET/MTJ-based Logic-In-Memory 7:2 compressor for high-speed application
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2022) Parmar, Rajdeep; Agrawal, Yash
    Spintronics can be a very good candidate for the replacement of complementary metal oxide-semiconductor (CMOS) technology. A digital signal processor (DSP) has a multiplier as a key element in the circuit. Multiplier having larger propagation delay becomes the bottleneck for the chip designed because of the component being in the critical path due to larger delay. So, the parallel multiplier is used to reduce the propagation delay in which partial products have to be added which can be done by the compressor. Compressors with less propagation delay give an advantage and are more efficient. This thesis work focuses on the 7:2 compressor which has 7 inputs and 2 outputs giving compression from 7 to 2. This proposed work is implemented using the Logic in memory architecture of spintronics. Given work uses magnetic tunnel junction (MTJ). This proposed work gives a lesser propagation delay compared to work. This work has a reduction of ~11.9% in the propagation delay with nearly PDP. This thesis work can also be used with logic in memory (LIM) architecture because of the Non volatile nature of the STT-MTJ. This proposed work is based on the FinFET/MTJ structure simulated on HSpice software with 16nm technology of FinFET. For a favorable comparison, the circuits are redesigned. The 7:2 compressor circuit proposed in is redesigned using the 16nm FinFET technology. This circuit based on solely FinFET is then compared with the FinFET/MTJ based hybrid structure. The performance benchmark of the given work gives 244.36ps of the 7:2 compressor. The performance benchmarking of the FinFET/MTJ based hybrid structure with the conventional 7:2 compressor shows an improvement in the propagation delay. Given the proposed 7:2 compressor will be used in the high-speed application multiplication. Although the application of the design is not limited to multiplication, it can also be used for image compression.
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    CMOS RFIC mixer design
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Gupta, Mukesh; Gupta, Sanjeev
    A CMOS RF (Radio Frequency) up/down conversion mixer results in a reasonable increase in transceiver integration and a reduction in cost. The design of mixers faces many compromises between conversion gain(GC), local oscillator (LO) power, linearity, noise figure (NF), port-to-port isolation, voltage scaling and power consumption. Mixer linearity is a very important parameter in transceiver design, because system linearity is often limited by the first down-conversion mixer due to a relatively large signal compared with that at the LNA input. Since active FET (Field Effect Transistor) mixers achieve conversion gain with lower LO power than their passive counterparts, the active CMOS single-balanced and double-balanced Gilbert mixers are commonly used in the CMOS transceiver design. Compared with the single-balanced counterpart, the double balanced mixer has better port-to- port isolation due to symmetrical architecture. The double-balanced mixer has a higher noise figure due to more noise generators. The overall Gilbert mixer linearity is controlled primarily by the transconductance stage if the LO-driven transistors act as good switches. This report describes a Gilbert cell mixer with source degeneration for 900 MHz frequency. The circuit converts a 900 MHz RF signal directly to base band [IF (Intermediate frequency) 45 MHz] using an 855 MHz LO frequency. The mixer uses common source MOSFETs with inductive degeneration to convert the input RF voltage to a current. This current is then steered using a switching network composed of MOSFETs that is driven with the LO and a 180 degree phase-shifted version of the LO. Gilbert Mixer achieves gain through an active predriver [The V-I (voltage to current) converter]. This V-I converter is highly nonlinear; hence, the Gilbert Mixer distortion performance is worse. This thesis tries to propose a simple linearity improvement technique for Gilbert Cell Mixer by including an additional capacitor located in parallel with the intrinsic gate-source capacitor of the common source transconductance stage. Also, to reduce the flicker noise of the switching transistors which depends on the frequency and circuit capacitance at the common source node of the switching stage, a method is used to reduce this capacitance by adding an extra inductor that helps for simultaneously match low 1/f noise, high linearity and low NF at the expense of Conversion gain. The design is based upon the third order intermodulation distortion (IM3) and output current equations of MOSFETs and flicker noise equation when it is subjected to an ac input signal. The performance has been verified using Agilent’ Advanced Design System (ADS) simulations. The designed mixer has a voltage conversion gain of 15.804 dB, NFSSB of 6.565 dB, NFDSB=3.975 dB, IIP3 of -1.158 dBm, OIP3 USB of 14.699 dBm, OIP3 LSB of 14.646 dBm, LO to IF isolation of -27.532 dB, LO to RF isolation of -69.365 dB and RF to IF isolation of -56.554 dB for single ended RF Input.
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    CMOS latched comparator design for analog to digital converters
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Gupta, Amit Kumar; Parikh, Chetan D.
    Conventional comparators are at the two extremes as far as power delay product and isolation between input and output is concern. Either they achieved very good isolation at the cost of power in the preamplifier or save the static power dissipation in preamplifier in the latching mode which increases the feed through. In this thesis work we propose an optimized CMOS Latch Comparator. The simulation result based on .18um technology, shows the working of the comparator at 500 MHz, with moderate power delay product and isolation compared with the conventional architecture.
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    Receiver amplifier design using CMOS current feedback amplifier and current conveyors
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Kaushik, Gaurav; Nagchoudhuri, Dipankar
    In the world of high-speed communications, systems involving high-speed data transfer require circuits with innovative features for good performance in terms of speed and power consumption. These data transfer systems constitute of large number of data channels each constituting of driver unit, transmission lines and a receiver unit. The receiver unit has small differential signals as the input. The designed receiver amplifier is required to have wide bandwidth, large slew rate and at the same time, capability to convert the differential input signal to single ended amplified signal without much distortion. For large number of data channels, it is also required that the power consumption of the receiver unit is minimal. In this work, a model for the receiver amplifier design is implemented using a closed loop amplifier and a differential to single ended converter. Current feedback amplifier is selected for the design of the closed loop amplifier due to their advantages over other topologies in high-speed design. Current feedback amplifiers have current on demand architecture that provides them dynamic current from the supply rails for charging or discharging load for large input signals. The differential to single ended converter is designed using two translinear positive second generation current conveyors. Translinear current conveyors due to their simple circuitry and dynamic current supply during large input signals are able to provide large bandwidth and low loss of signal resulting in very high-speed signal processing. The amplifier model is implemented in MOSIS 0.5 µm single-well technology using BSIM 3.0 model parameters. The obtained results are discussed in the end along with comments on the performance of the current mode circuits involved – current feedback amplifier and current conveyor.
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    Low power high slew-rate adaptive biasing circuit for CMOS amplifiers
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Rao, A. Narayana; Parikh, Chetan D.
    Adaptive biasing technique in analog and mixed signal integrated circuit design is used mainly to reduce the power and improve the driving capability. It has found many applications, like power amplifiers in RF communication systems whose biasing current is adjusted based on the detected input RF signal level. In RF tuning circuits filters can be automatically tuned simply by varying the bias current of the transconductance amplifier with respect to the control voltage. Existing techniques uses different methods like dynamically switching the current, using feed back, etc. Some of these are area efficient techniques and some are power efficient techniques. In this work, a new adaptive biasing scheme is proposed which shows excellent results in terms of both area and power without affecting amplifier design. It uses a simple input pair to sense input signals, current mirrors to generate a difference between two currents, this difference in current varies linearly with the input signal while nonlinearity is cancelled out. Simulation results shows about 80% of quiescent power can be saved while maintaining the amplifier small signal characteristics.
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    Novel architecture for a CMOS low noise amplifier at 2.4 GHz
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2005) Ray, Anuradha; Parikh, Chetan D.
    Radio frequency design has been one of the major research areas in the recent past. Emergence of several Wireless Communication standards has demanded availability of different analog blocks for use in transceivers with different constraints, imposed by the nature of application. Particularly, lot of research has been carried out in CMOS technology, due to its low cost nature. LNA is one of the most important building blocks in the front end of the wireless communication systems. It determines the noise performance of the overall system, as it is the first block after the antenna. With technology scaling, the transistor’s cut off frequency continues to increase, which is desirable for improving the noise performance of CMOS circuit. Some other advantages like low cost, high level of integration motivates research of RF modules using CMOS technology. In recent years valuable research is done on CMOS LNA design in submicron technologies: from topology investigation to various new ideas on improvement of low power consumption, low noise figure, high gain, smaller space and low supply voltage. In this thesis, a new LNA architecture is reported, that consumes less power compared to other existing architectures, while providing the same gain, noise figure, CP-1dB and IIP3 figures. The new architecture achieves this better performance by combining the beneficial properties of two existing architectures – Lee’s inductive input stage, and the current-reuse (or the CMOS inverter amplifier) architecture. Detailed design procedures, and Spice simulation results are presented in the thesis, along with a brief survey of noise sources in MOSFETs, and a literature survey of existing LNA architectures.