M Tech Dissertations
Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3
Browse
11 results
Search Results
Item Open Access Design of a low noise amplifier for UWB range of 5.5-8.5 GHz(Dhirubhai Ambani Institute of Information and Communication Technology, 2014) Vyas, Krunal D.; Gupta, SanjeevThis study reviews and analyze the designing of Low Noise Amplifier. The parameters should be analyzed properly before the design of LNA, so this thesis includes the basics of all parameters with transmission line usage as inductor and capacitor. The first phase of thesis includes the method to designing and simulation of LNA at 5.8GHz frequency from reference. In this thesis, amplifier used is Ga-AS type where as in reference paper superHEMT was used. The method for designing LNA includes impedance matching with normalized impedance and admittance and also using microstrip lines. With the help of Stability circles one can design proper amplifier at particular frequency. Finally the simulation of LNA for 5.8 GHz has been done in Agilent ADS software version 2009 with the results of gain, NF, stability factor which is different from reference. The second phase of thesis includes the method to designing and simulation of LNA in 5.5 GHz -8.5 GHz. In this thesis, transistor used is NE3512S02 which covers desired frequency range with proper gain and noise figure. The method for designing LNA includes impedance matching with normalized impedance and admittance and also using microstrip lines. Finally the simulation of LNA in 5.5-8.5 GHz has been done in ADS software with the results of gain, NF, stability factor.Item Open Access Column decoder for memory redundant cell array(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Nahar, Pinky; Nagchoudhuri, DipankarAs the semiconductor technology advances, the yield of memory chip is reducing. The cause of yield degradation is errors in manufacturing process associated with tight geometries. The thesis work proposes a redundancy circuit to enhance the reliability for the faulty columns in memory array. The online testing circuit generates the signals for faulty columns, which enables the redundant circuit to replace faulty with spare column of cells. The redundant decoder and multiplexer provide the path to replace the faulty columns with the spare columns. The novel feature of proposed work is that, input of redundant column decoders depends upon the number of bits for a word output instead of the address signals. The proposed circuit provides the reliability with some loss in speed and overhead in terms of chip area. The operating voltage for the design is 3V. The layout and simulations are performed in CADENCE tool for .1μm technology. The performance parameters of various decoders are performed in LT Spice for .18μm technology.Item Open Access Bidirectional service composition(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Khakhkhar, Sandip; Chaudhary, SanjayService is a network addressable software component to perform a specific task. A service consumes given input parameters, performs specific task based on input parameters and returns the result in terms of output parameters. A service request specifies required task in terms of input parameters that can be provided and output parameters that are required. A service discovery mechanism can be used to find services that can be executed to satisfy service request. Service and service request is match by comparing their input/output parameters. A service request may be complex enough that it can not be satisfied by an individual service. It might be possible to execute a chain of services in a particular order to satisfy service request. This chain of services is referred as composition plan and service offered by executing this composition plan is referred as composite service. The aim of service composition algorithm is to generate a composition plan and generate composite service to satisfy service request. Services involved in composition plan are selected manually while designing composite service in static composition process. This process consumes considerable amount of time and effort. It is also vulnerable to changes in input/output of services. A dynamic composition algorithm is required that can automatically select services involved in composite plan and generate a composite service on-the-fly. Main issue with dynamic composition algorithms is composition time taken by algorithm to generate a composite service. Composition time indicates duration of the time at which the service request was submitted to the algorithm till the algorithm generate a composite service that can satisfy service request. Composition time depends upon the number of services required to explore in order to find services that can take part in composite plan. Dynamic composition algorithms presented in previous work mainly follows either forward chaining approach or backward chaining approach to find a composite service. Performance of algorithms based on forward chaining approach or backward chaining approach suffers for certain cases to generate a composite service where number of services explored increases exponentially as number of iterations increases. This work proposes a dynamic composition algorithm that gives consistent performance across all the cases. Proposed algorithm approaches from two directions alternatively, one follows forward chaining approach and other follows backward chaining approach. Composition algorithm following only forward chaining approach or backward chaining approach performs all the iterations in one direction only where as proposed algorithm requires only half number of iterations in both directions. Algorithm uses two types of matching strategy to compare input/output parameters. First one is based on keyword matching and second one based on semantic matching strategy. Performance of proposed algorithm is evaluated by performing relevant experiments and results are compared with algorithms based on only forward chaining approach or backward chaining approach. Proposed algorithm explores less number of services and takes less composition time compared to algorithms based on only forward chaining approach or backward chaining approach.Item Open Access High-performance low-voltage current mirror design(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Gandhi, Nikunj; Parikh, Chetan D.Design of high precision analog circuits requires accounting for the mismatch between nominally identical transistors. In this work, errors affecting CMOS current mirrors due to mismatch between identical transistors are discussed, and circuit techniques to overcome these errors are studied. The dynamic current mirror (DCM) is one of the solutions to overcome mismatch problems. Dynamic current mirrors contain analog and digital components together so that errors due to process variations, temperature and ageing effect can be cancelled. Various circuit techniques such as op-amp based DCM, reduced transconductance based DCM, and cascode based DCM have been used to improve the performance of current mirrors. This thesis proposes a novel circuit for a low-voltage high-performance dynamic current mirror design. The thesis investigates the performance of analog switches at low voltages, and suggests an improved bootstrap switch; errors due to clock feed through and charge injection in the switch are analysed. A new low charge injection, voltage-boosted analog switch is recommended in the dynamic current mirror design. A bulk-driven dynamic current mirror circuit is proposed, and found to be an effective solution at low voltage. The proposed circuit is designed optimally in a 0.18µm CMOS process, in the Cadence Spectre environment. A current copying accuracy of ±0.14% is achieved under worst case conditions.Item Open Access High speed sample and hold circuit design(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Dwivedi, Varun Kumar; Parikh, Chetan D.Sampling of the time-varying input signal is the first step in any type of Analog to Digital (A/D) conversion. For Low Power and high-speed A/D converter, a high-performance Sample and Hold (S/H) circuit is needed as its front-end component. In this thesis, the high speed sample and hold circuit has been designed, requiring low power as a front end block of pipeline analog to digital converter. In this work, architectures of sample and hold circuit are studied and issues which limit the performance of sample and hold circuits are discussed. A fully differential S/H circuit using bottom plate sampling is proposed. The circuit has been designed in order to meet the specification. Amplifiers are studied and folded-cascode amplifier is chosen as an optimum architecture for switch capacitor based sample and hold circuit. The proposed circuit is designed optimally in a 180 nm CMOS process, in the Cadence Spectre environment. The speed and power achieved are 125 MSPS, 6.8mW respectively.Item Open Access Executable specification design and simulation of OFDM based communication system(Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Sa, Sudhir Kumar; Dubey, RahulThe communication system using the OFDM principle is today one of the most important application in communication field. This system has various applications from broadband to 3G and digital TV to Radio LANs. This master’s thesis project deals with the implementation of certain specification, algorithmic exploration for WVAN (wireless video area network) in Simulink®. The implemented model and its specification is the reference for the hardware designing and verification. The model used in OFDM based QPSK/16-QAM modulated communication system for the WHD WVAN standard at the High Rate Physical (HRP) layer. This thesis project describes the functionality of the various communication blocks and the method of data transmission through these blocks. The main purpose of this model is to calculate the BER (Bit Error Rate). The final design which supports the different HRP mode for different code rate and different Modulation scheme can take different length of sub-packets which depends on the HRP mode of Transmission. This model also implements the radix-2 FFT algorithm for fixed point FFT processor. Since the FFT processor cannot be used standalone, so in this thesis it is employed in an OFDM Transmitter and Receiver. The goal of this report is to outline the knowledge gained during the master’s thesis project, to describe a design methodology for the OFDM based communication system for high throughput and best error protection. The functionality of each block of the communication system is written in „C‟ code and the output data of each block of Simulink Model is compared to 'C' code written output for the same input.Item Open Access Design and implementation of 128-point fixed point streaming FFT processor for OFDM based communication system(Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Verma, Sunil Kumar; Dubey, RahulFast Fourier Transform (FFT) processors are today one of the most important blocks in communication systems. They are used in every communication system from broadband to 3G and digital TV to Radio LANs. This master’s thesis project deals with the pipelined, radix-2 algorithmic exploration and the hardware solution for the FFT processor with the FFT size of 2N points, the selection of the scaling schemes based on application requirement is discussed. The designed architecture is functionally verified in Simulink® and the Xilinx® ISE simulator. How to encapsulate the C++ coded algorithms or functions into the Simulink. This FFT processor is used in OFDM based BPSK modulated communication system for the WHD WVAN standard at the Low Rate Physical (LRP) lay. This thesis project presents the design of the 128 point fixed–point F streaming processor. The final architecture used is the SDF (single path with delay feedback) that implements the radix-2 FFT algorithm. Since the FFT processor can’t be used standalone, so in this thesis it is employed in an OFDM Transmitter and the performance is measured for SNR over a range of PAPRs. The goal of this report is to outline the knowledge gained during the master’s thesis project, to describe a design methodology for the fixed point pipelined FFT processors, the scaling choices and how to encapsulate the existing C code into the Simulink environment to measure the performance of fixed-point systems.Item Open Access Pulse shaping design for PAPR reduction in OFDM(Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Jain, Akansha; Vijaykumar, ChakkaFuture mobile communications systems reaching for ever increasing data rates require higher bandwidths than those typical used in todays cellular systems. By going to higher bandwidth the (for low bandwidth) at fading radio channel becomes frequency selective and time dispersive. Due to its inherent robustness against time dispersion Orthogonal Frequency Division Multiplex (OFDM) is an attractive candidate for such future mobile communication systems. OFDM partitions he available bandwidth into many subchannels with much lower bandwidth. Such a narrowband subchannel experiences now almost at fading channel. However, one potential drawback with OFDM modulation is the high Peak to Average power Ratio (PAPR) of the transmitted signal: The signal transmitted by the OFDM system is the superposition of all signals transmitted in the narrowband subchannels. The transmit signal has then due to the central limit theorem a Gaussian distribution leading to high peak values compared to the average power. system design not taking this into account will have a high clip rate. Each signal sample that is beyond the saturation limit of the power amplier suersither clipping to this limit value or other non- linear distortion, both creating additional bit errors in the receiver. One possibility to avoid clipping is to design he system for very high signal peaks. However, this approach leads to very high power consumption (since the power amplifier must have high supply rails) and also complex power amplifiers. The preferred solution is therefore to apply digital signal processing that reduces such high peak values in the transmitted signal thus voiding clipping. These methods are commonly referred to as PAPR reduction. APR reduction methods can be categorized into transparent methods here the receiver is not aware of the reduction scheme applied by the transmitter and on-transparent methods where the receiver needs to know the PAPR algorithm applied by the transmitter. This master thesis would focus on transparent PAPR reduction algorithms. The pulse shaping mechanism is used to reduce PAPR. he ct is analyzed in terms of BER.Item Open Access High-speed 512-point FFT single-chip processor architecture(Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Sinha, Ajay Kumar; Nagchoudhuri, Dipankar; Mandal, Sushanta KumarThis thesis present a fully parallel novel fixed point 16-bit word width 512 point FFT processor architecture. The 512 point FFT is realized by decomposing it into three 8 point FFT units. This approach reduces the number of required complex multiplication compared to the conventional radix-2 512 point FFT algorithm. It uses an ROM unit for storing the twiddle factor. The proposed architecture is designed in XILINX 8.2i using Verilog and it is functionally verified with the MATLAB. The floorplanning and timing estimation of each basic module of the proposed architecture is done based on the macro element at 0.25 CMOS technology. The core area of this chip is 99.02 mm2. The processor compute one parallel to parallel (i.e. when all input data are available in parallel and all output data are generated in parallel) 512-point FFT computation in 422 clock pulse in 4.69sec at 90 MHz operation.Item Open Access Low power SRAM design(Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Bambhaniya, Prashant; Dubey, RahulIn the past, power dissipation was not constraining factor because of device density and operating frequency was low enough. But nowadays due to increased integration and operating frequency of integrated circuits, power consumption has become an important factor. Battery operated portable devices which performing the high performance processing task also consumes lots of power. The various methodologies are used to reduce the power dissipation by optimizing the parameters that are related to power consumption of circuit. The Static RAM is used as a cache memory in the processor and also has an application in the embedded system. Due to continuous advances in the integrated circuit technology, the density of SRAMs in embedded application has grown substantially in recent years. The SRAM block is becoming indispensable block in the system-on-chips (SoCs). The larger density SRAM block has a highly capacitive bit lines and data lines. The dynamic power of SRAM is mainly due to charging and discharging of highly capacitive lines. To perform the write operation in the SRAM cell to flip the data value, nearly full voltage swings is required on the bit line. This full voltage swing on the highly capacitive bit lines will consumes a greater amount power according to law of CV2f. Thus voltage swing reduction is an effective way to decrease the power dissipation. The current mode sensing technique is proposed to give the small voltage swing on the bit lines during write operation. In the proposed method the layout and simulation is done for the one bit line pair for three different methodologies. The bit line interference of selected cell with adjacent selected and non selected cell is also checked out. The proposed current conveyor method has shown an improvement in terms power dissipation over the voltage write and current read (VWCR) and current write and current read (CWCR) method without comprising the performance.