M Tech Dissertations

Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3

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    Low power SAR ADC with split capacitor DAC
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2013) Dhalvaniya, Pankaj; Sen, Subhajit
    Analog to Digital convertor and Digital to Analog convertors plays a vital role in Mixed Signal Design. Nowadays, the demand for designing of Low power, Moderate Resolution ADCs are increasing for Bio-medical applications and wireless sensor network application. SAR ADC is preferred for these kind applications. Comparator an important block, is most power consumer block in the SAR ADC. Resolution of SAR ADC is limited by the ratio error and parasitic capacitance of DAC capacitor. Also, the resolution of SAR ADC increases, area of the DAC increases and so does the power consumption.

    In this thesis work a 12-Bit, low power Differential SAR ADC with Split capacitor DAC is implemented in UMC0.18μm CMOS technology. Differential architecture is implemented as it has good noise immunity than the single ended architecture. In order to design lower SAR-ADC, Dynamic regenerative latch comparator is implemented and the pre-amplifiers used in the comparator, that are biased in sub-threshold region. Split capacitor DAC is used to reduce the capacitances, the area of the DAC. For high resolution SAR ADC, calibration of the capacitor is DAC necessary. In this thesis, digital domain calibration of split capacitor DAC and Analog domain calibration of BWC DAC is explained. Implemented architecture works at 1.8V power supply, 110KS/s and consume 30.7μW power. 12 Bit low power Differential SAR ADC with Split capacitor DAC is implemented in UMC0.18μm technology and simulation is done in Cadence Virtuoso 6.1 simulator.

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    Bidding strategies for dynamic spectrum allocation
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Dhumal, Neha; Srivastava, Sanjay
    Dynamic Spectrum Allocation is the process of assigning spectrum licenses in terms of the chunks of the spectrum band to the Wireless Service Providers (WSPs). This allocation assignment is being done as per the WSPs' requirement and this in turn would depend on the end users' applications demand [16]. For Dynamic Spectrum Access, economic framework is needed to make the system feasible under economic terms. This process uses some kind of service pricing mechanism that the service provider can use for the acquisition of the spectrum band and requirement of the end users.

    In the Dynamic Spectrum Allocation scenario, the problem is to find the appropriate bidding strategies. The approach to this problem is to simulate the different cases with varying parameters. Here, the interaction between the spectrum owner and providers is modeled through auction model which has been studied in this work whereas the interaction between the providers and end users is based on the demand. This thesis presents the bidding strategies and appropriate prediction method that maximize the revenue and the profit of both the providers as well as the end users. The auction method and different bidding strategies adopted, gives the winning criteria for the providers on how many number of units to bid and the prices for these units. Prediction method for the price uses the concept of probability of winning the particular unit. Simulation results show the comparison between prediction and actual values, revenue and profits of the providers. Among the different auction and bidding methods, the Vickrey auction has been used in this work. In the Vickrey auction method, the allocation of the resources is done efficiently as compared to other methods and does provide dominant bidding strategy.

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    Investigation on multi-band fractal antennas for satellite applications
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Shah, Milind; Gupta, Sanjeev
    Remote sensing is a very important application of satellite communication. In remote sensing applications, multiple frequencies are utilized. Use of different antennas for different frequencies is a complex task and so use of single multiband antenna is desirable. Fractal geometries can be utilized to design single multiband antenna operating at various required frequencies which may be widely separated and non-harmonically related. In this thesis fractal geometry concept has been utilized to achieve multiband and compact design. Here multifractal cantor geometry is used due to its simple construction and ease in tuning. In addition to multiband behavior, the antenna must provide sufficient bandwidth. Unfortunately the microstrip antennas are having very narrow bandwidth. There are other techniques to increase bandwidth such as aperture coupled structure or electromagnetically coupled structure. But these solutions result in the complex multilayer structure. To prevent this complexity and to increase bandwidth, monopole structure has been utilized. Usually for satellite communication 28 dB to 32 dB gain is required. To fulfill this requirement, an array using multiband element is also designed.
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    Statistical co-analysis, robust optimization and diagnosis of USB 2.0 system for signal and power integrity
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Tripathi, Jai Narayan; Dubey, Rahul
    Signal Integrity (SI) and Power Integrity (PI) are the most critical issues as semiconductor industry is moving towards higher operational speeds. Signal integrity and power integrity are such issues that should be looked at system level rather than looking at active and passive networks separately. System level analysis becomes a necessity when the individual subsystems work according to specifications, and even after that complete system doesn't work well. System level signal integrity and power integrity problems for high speed serial links have been taken into account in this thesis. Serial links are being used more and more rather than parallel links due to lesser skew and lower pin counts. Specifically USB 2.0 IP is used for this thesis work, but the analysis is generic for all serial links. This thesis considers SI and PI as a dual and a common model is used which considers both SI and PI. A statistical co-analysis of SI and PI for high speed serial links is used, which can be used for a cost effective solution too. Statistical methods are used for efficient simulations and to extract maximum information contents in the least simulation combinations. Based on this co-analysis, the system is diagnosed or modified for better SI and PI. In the end, reflection gain concept is also taken in to account for the diagnosis of the system. All in all, USB 2.0 system is diagnosed for better SI and PI. System level robustness analysis of high speed serial links are taken into account with effect of external environment. A strong correlation between measured and simulated results is shown. A generic methodology for SI and PI for high speed serial links is presented with complete analysis of package, board, termination, squidd card, decoupling network etc..
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    Design of multi-band fractal antenna for satellite navigation application
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Pathak, Swapna; Gupta, Sanjeev
    Recent efforts by several researchers around the world to combine fractal geometry with electromagnetic theory have led to a plethora of new and innovative antenna designs. This research proposal has been primarily focused in the analysis and design of fractal antenna elements. Fractals have no characteristic size, and are generally composed of many copies of themselves at different scales. These unique properties of fractals will be exploited in order to develop a new class of antenna-element designs that are multi-band and/or compact in size. These key issues are the major motivations for the research project which involves the analysis and design fractal antennas in L, S and C-bands.
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    Design of low power and high speed decoder for 1MB memory
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Gupta, Punam Sen; Nagchoudhuri, Dipankar
    Technology scaling is accompanied by rise in leakage power dissipation. This thesis proposes a voltage controllable circuit in the feedback path of the decoder, which drastically reduces the standby leakage current with minimum loss in speed and slightly overheads in terms of chip area. This circuit generates slightly lower supply voltage when the load circuitry is in the standby mode thereby raises the Vt of the CMOS transistors and hence reduces leakage power dissipation The overall power dissipation of a 7x128 decoder is reduced from 0.928mW to 0.584mW for 1Mb Memory with voltage controllable circuit, namely 37% lowering in power dissipation. The operating voltage for the design is 1.2 V. Layout is done in magic 7.1 version in 180nm technology. The simulations are done in LT spice.
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    Design of a CMOS variable gain amplifier
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Verma, Vivek; Parikh, Chetan D.
    In advanced CMOS technologies as device dimensions are decreasing, requirement for lower supply voltages are increasing to make certain device reliability. So, challenges for analog circuit designers are to discover new techniques to design analog circuits that can operate at lower supply voltages with desired performances. Another challenge for designer is to design a circuit with less power consumption while maintaining desired performance. In this thesis, a CMOS variable gain amplifier is designed to target above challenges. A fully differential, CMOS variable gain amplifier (VGA) has been designed for a 1.2- volt, low-power, 57-dB dynamic range, and high bandwidth. The VGA comprises of a control circuit, variable gain stages with common-mode feedback circuit. The gain of the VGA varies dB-linearly from -32 to 25 dB with respect to the control voltage, VC. Proposed VGA uses common-mode feedback (CMFB) circuit to fix and stabilize the output DC levels at a particular voltage depending on the input common-mode range (ICMR) requirement and output swing of the VGA. The proposed VGA uses capacitive neutralization technique to achieve high bandwidth operation. This VGA draws 1.25 mA current from a 1.2 V supply. The 3-dB bandwidth varies from 110 MHZ (at 25 dB gain) to 3828 MHz (at -32 dB gain). The proposed VGA is simulated for 0.18μm CMOS technology in LT-Spice with BSIM3V3 model.
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    Design of low-voltage, low-power, wide-band CMOS LC VCO using active inductors
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Sesha Sai, Aduru Venkata Raghava; Parikh, Chetan D.
    In this thesis the design of low-voltage, low-power, wide-band CMOS LC VCO using active inductor has been proposed. The oscillator is based upon the classic LC-tuned negative-resistance topology, with a novel active inductor using a low-voltage gyrator topology with a feedback resistance, where feedback resistance is realized by a NMOS operating in triode region whose bias voltage tunes the inductance of the active inductor and hence the frequency of VCO. The simulation results shows that this VCO operates in a 1.19 GHz to 2.49 GHz , while consuming 1.09 mW from a 1.2V power supply. The VCO’s phase noise level is -86.9 dBc/Hz at 1 MHz offset from a 1.55 GHz carrier. The deviation of the phase noise is 11.5 dBc/Hz during this tuning range. All the circuit simulations of VCO were simulated in SpectreRF using TSMC 0.18μm CMOS technology.
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    Design of low voltage high performance voltage controlled oscillator
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Ramesh, R; Nagchoudhuri, Dipankar; Mandal, Sushanta Kumar
    In this thesis an ultra low voltage differential capacitive feedback VCO is being proposed .The VCO operates at very low supply voltage of 0.6V.The VCO uses techniques like Forward Body Bias (FBB), and capacitive feedback to achieve high performance in terms of phase noise and output voltage swing. It uses differential MOS varactors for frequency tuning due to which all low frequency noise such as flicker noise gets rejected. Inductor was designed and it was simulated in IE3D electromagnetic simulator to achieve good Quality factor. This VCO achieves a very low phase noise of -119dBc/Hz@1-MHz offset frequency, power consumption of 3.27mW, and tuning range of 6% .All the circuit simulations of VCO were simulated in SpectreRF using TSMC 0.18μm CMOS technology
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    Symbol detection in MIMO systems
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Dhaka, Kalpana; Chakka, Vijaykumar
    Multiple input multiple output symbol detection methods are observed under frequency flat fading AWGN channel condition. The modulation method employed is Quadrature amplitude modulation (QAM). The various symbol detection techniques are compared to observe their behavior under AWGN channel condition condition. Maximum likelihood (ML) symbol detection method gives the best performance but because of its high complexity it can’t be used. Sphere decoder reduces the complexity to some extent providing similar performance as ML estimate. The other methods used are Zero forcing and Minimum mean square stimation. These two methods when used successively for interference cancellation improves performance to large extent along with reduction in the cost. The technique employed for successive detectionis devised by bell laboratory hence it is called as V-BLAST method. Maximum a posteriori when used along with V-BLAST MMSE algorithm further improves the performance. These methods even works well under Rayleigh channel condition. Finally, the simulation results for performance of V-BLAST under both the channel condition are observed for all the symbol detection techniques. To increase the diversity for improved performance space time trellis code are employed. Their performance is observed for QPSK modulation scheme.