M Tech Dissertations

Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3

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Subject: search.filters.subject.Energy conservation

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    Power management of wireless sensor node by dynamic power measurement
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2011) Kapasi, Jay; Ranjan, Prabhat
    Wireless sensor network(WSN) is a collection of spatially distributed autonomous sensor nodes, which cooperatively monitor physical or environmental conditions, such as temperature, sound, vibration, pressure, motion or pollutants. As Wireless sensor node cannot be connected to a large source of power supply, they have to run on portable energy sources such as solar cell and batteries. Thus it is very important to minimize the use of power in each individual node of network as even a single point of power failure may prove to be a great loss of functionality. Even though minimization of power consumption may appear to be a complex problem, due to advances in technology and availability of devices with different low power states, it has become a simplified matter of just determining the power state of each device in system to minimize power consumption. The work presented here shows an implementation of a power aware wireless sensor network. Power is measured dynamically in sensor node as certain events trigger the addition of new loads.
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    Effect of location inaccuracy on deterministic coverage and connectivity protocol in wireless sensor network
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2011) Jain, Poonam; Srivastava, Sanjay
    Sensor networks have a wide range of potential, practical and useful applications. Energy saving is one critical issue for sensor networks since most sensors are equipped with non rechargeable batteries that have limited lifetime. Many of the current literature of Energy efficient scheduling protocols assumed that sensing range of a sensor node is always uniform in all directions (unitdisc model). Unfortunately, this is not appropriate for the realistic sensing model, as the sensing capabilities of networked sensors are affected by environmental factors. The other issue is that most of the protocol used the location information of sensors for accurate data analysis. GPS technology and localization algorithms provide location information. But these technologies do not give accurate information, there is some uncertainty or error is exist in location information. Most of the protocols are location depended and will not work efficiently when inaccurate information is given. The main goal of this work is to analyze the performance of deterministic energy efficient scheduling protocol with location inaccuracy.
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    Design methodology for architecting application specific instruction set processor
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Desai, Meghana; Dubey, Rahul
    Application Specific Instruction-set Processors (ASIP), also referred as extensible processors, represent the state-of-the-art microprocessor architecture. ASIPs are practically leading towards the realization of System-on-a-Chip (SoC) concept; as processor, customised for an application, can be easily integrated in a SoC as pre-designed and pre-verified soft RTL block. Most significant and challenging part for these flexible or programmable processors is the design methodology. The challenge lies in providing a simple configurable design space such that the outcome is optimised, efficient and customised application specific processor hardware, with very short design cycle time. The bottle neck for a processor is chiefly the data path design, as it has computational intensive functional units which add to the major portion of hardware area along with timing. In case of ASIP as well, data path modification is to be achieved as per the requirements. Current electronic design automation (EDA) tools are intelligent and if exploited well can actually help in providing various optimizations in the design. The implemented design approach is based on these aspects of selection of accurate data path elements along with distributed control path and exploiting the inbuilt functionality of EDA tools for generating user defined architecture. In this project a non-pipelined as well as five stage pipelined processor fabrics are implemented with configurable parameters. A library of basic arithmetic functional units is created from which a component of desired characteristic is selected and integrated in the data path. Synthesis of modified processor core is performed with a set of constraints to achieve required trade off between area, power and timing. Multi-supply voltage feature of the synthesis tool is exploited to meet the timing closure of the generated processor core.
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    Low power microprocessor design
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Bhatt, Vishal; Dubey, Rahul
    This research work tries to reduce the power consumption of a processor with signal processing features. For low power design, focus is on developing ‘Low power synthesizable Register File’, as the initial study shows that there is potential for significant benefit by doing this. Two techniques are proposed and implemented in this work, (1) Compiler Driven Register Access (CDRA) (2) Register Windowing. Here, Register Windowing is an extension to an earlier technique called ‘Register Isolation’. Benchmarks used for evaluating design in terms of power consumption and performance, simulate conditions encountered by the processor in control and DSP applications. After applying various low power techniques, average power reduction obtained across benchmarks is 1.5% and the maximum power reduction obtained is 2.6% when compared to Base Processor which is a customized version of MIPS architecture with signal processing capability.
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    Energy conserving voidless coverage in wireless ad-hoc sensor networks
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2005) Vege, Hari Kiran; Ranjan, Prabhat
    For many sensor network applications such as intrusion detection and military surveillance, it is necessary to provide full sensing coverage to a security-sensitive area while at the same time minimizing energy consumption and extending system lifetime by leveraging the redundant deployment of sensor nodes. It is also preferable for the sensor network to provide surveillance service for target areas with different degrees of security requirements. In this thesis, an established scheme that aims at adaptable energy-effect sensing coverage is analyzed. In this scheme, each node is able to decide a schedule for itself to guarantee a certain degree of coverage (DOC) with average energy consumption inversely proportional to the node density. An enhancement to this scheme is suggested. The validity of the proposed extension is proved though the simulations that address the issues of total energy consumption, balance of energy consumption, half-life of the network, coverage percentage over time, energy consumption for α coverage and actual degree of coverage. Comparisons are made with the two existing schemes namely ‘Adaptable Sensing Coverage Scheme’ and Sponsored Coverage Scheme’. These simulations show that the proposed scheme accomplishes α-coverage surveillance with low energy consumption. It outperforms other state-of –art schemes by as much as 50% reduction in energy consumption and as 130% increase in the half-life of the network.