M Tech Dissertations

Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3

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Subject: search.filters.subject.Image compression

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    ItemOpen Access
    Super-resolution of hyperspectral images
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2011) Bhimani, Amitkumar H.; Joshi, Manjunath V.
    Hyperspectral (HS) images are used for space areal application, target detection and remote sensing application. HS images are very rich in spectral resolution but at a cost of spatial resolution. HS images generated by airborne sensors like the NASA’s Airborne Visible/Infrared Imaging Spectrometer (AVIRIS) from satellites like NASA’s Hyperion. We proposed a principal component analysis (PCA) based learning method to increase a spatial resolution of HS images. For spatial resolution enhancement of HS images we need to employ a technique to increase the resolution. We used PCA based approach by learning the details from database which consist of high spatial resolution satellite images. Super-resolution, is an ill-posed problem, and does not result to unique solution, and therefore it is necessary to regularize the solution by imposing some additional constraint to restrict the solution space. To reduce the computational complexity, minimization of the regularized cost function is done using the iterative gradient descent algorithm. In this report the effectiveness of proposed scheme is demonstrated by conducting experiments on both Multispectral (MS) and Hyperspectral real data. The HS and MS images of AVIRIS and Digital airborne Imaging spectrometer (DAIS) respectively used as input for super resolution (SR).
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    ItemOpen Access
    FPGA implementation of image compression algorithm using wavelet transform
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Rawat, Nitin; Dubey, Rahul
    This work presents FPGA implementation of image compression algorithm by using wavelet transform. Here the emphasis has been made on algorithmic encoding, the first step of image compression problem. The transform that has been used for algorithmic encoding is the „Discrete Wavelet transform‟. The Wavelet family which has been used for this purpose is the „Haar Wavelet family. Various issues involved in hardware implementation of Wavelet Transform such as fractional interpretation, signed Q-format, range of gray scale values, memory requirement and addressing schemes have been discussed. A functional unit has been proposed which calculates the Wavelet transform of input pixel values. An efficient use of „Block RAM‟ present in FPGA has been proposed by placing the initial pixel values and then placing the computed Wavelet transform values back in this memory itself. A suitable way to tackle the issue of storing intermediate wavelet transform values by using a buffer memory has been suggested. This removes the need of having an external memory and thus the time required in accessing this memory reduces drastically. A special emphasis in order to use this memory in accordance with the requirement of image processing algorithms has been made by deriving the necessary addressing schemes. This is done in order to have the correct placement of transformed values in memory. Here we have used the Dual port feature of the Block RAM with one port providing multiple pixel values to the functional unit and other being used to write transformed values one at a time. Along with this, the DCM available in FPGA has been used to address issue of skew and „set up time‟ involved with the clocks in digital design. A delayed version of system clock is sent to memory so that all addresses and enable signals calculated with reference to system clock are stable when active edge of clock is received by memory. All these modules are incorporated in a top module which provides the Wavelet transform of an image. The modelling of the architecture has been done by using Verilog Hardware Description Language and the functional simulation has been done by using Xilinx ISE Simulator. The synthesis of the design has been done by using Xilinx Synthesis Tool (XST) of Xilinx. The total amount of the resources being utilized is reported and it comes out well within reach of Spartan 3E FPGA, our target device. The maximum clock frequency which can be used for the design comes out to be 23 MHz which is quite high for a compute intensive algorithm like Discrete Wavelet Transform.
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    ItemOpen Access
    Fractal based approach for face recognition
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2004) Athale, Suprita; Mitra, Suman K.
    An automated face recognition system is proposed in this dissertation. The system efficiently recognizes a candidate (test) image using the interdependence of the pixel that arises from the fractal compression of the image. The interdependence of the pixels is inherent within the fractal code in the form of chain of pixels. The mechanism of capturing these chains from the fractal codes is called pixel chaining. The present face recognition system tries to match pixel chains of the candidate image with that of the images present in the database. The work domain of the system is fractal codes but not the images. This leads to an advantage towards handling large database of face images.

    The system performance is found to be very satisfactory with the recognition rate of 98.4%. A minor improvement in the performance of the system over a few existing methods has been observed.