M Tech Dissertations
Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3
Browse
10 results
Search Results
Item Open Access Analysis of charge injection in a MOS analog switch with impedance on source side(Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Rao, D. Srinivas; Sen, SubhajitTurning off of a transistor introduces error voltage at the output of Sample and Hold circuits which are the key components of Analog to Digital Converters (ADCs) and hence limits their accuracy of performance in high switching applications. The error voltage at output is mainly caused because of charge injection due to the carriers released from the channel and due to coupling through gate-to diffusion overlap capacitances. Hence, in order to fully understand the behaviour of charge injection in the presence of source impedance, a device is modelled and simulated in Pisces. This thesis is about modelling of an N-type Metal Oxide Semiconductor (NMOS) device in Pisces Postmini Tool with a hold capacitor on drain side, so that it can be used as a CMOS Analog switch. The main aim is to analyze the trends in output error voltage in the presence of source resistance. The output error caused due to charge injection is examined as a function of different parameters like gate voltage fall time, source resistance, input voltage, substrate concentration etc. Test structures similar to the one modelled in Pisces is simulated in 0.18μm CMOS technology for the verification purpose. It is shown that the modelled and simulated results exhibit good trend agreement.Item Open Access High-performance low-voltage current mirror design(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Gandhi, Nikunj; Parikh, Chetan D.Design of high precision analog circuits requires accounting for the mismatch between nominally identical transistors. In this work, errors affecting CMOS current mirrors due to mismatch between identical transistors are discussed, and circuit techniques to overcome these errors are studied. The dynamic current mirror (DCM) is one of the solutions to overcome mismatch problems. Dynamic current mirrors contain analog and digital components together so that errors due to process variations, temperature and ageing effect can be cancelled. Various circuit techniques such as op-amp based DCM, reduced transconductance based DCM, and cascode based DCM have been used to improve the performance of current mirrors. This thesis proposes a novel circuit for a low-voltage high-performance dynamic current mirror design. The thesis investigates the performance of analog switches at low voltages, and suggests an improved bootstrap switch; errors due to clock feed through and charge injection in the switch are analysed. A new low charge injection, voltage-boosted analog switch is recommended in the dynamic current mirror design. A bulk-driven dynamic current mirror circuit is proposed, and found to be an effective solution at low voltage. The proposed circuit is designed optimally in a 0.18µm CMOS process, in the Cadence Spectre environment. A current copying accuracy of ±0.14% is achieved under worst case conditions.Item Open Access Particle swarm optimization based synthesis of analog circuits using neural network performance macromodels(Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Saxena, Neha; Mandal, Sushanta KumarThis thesis presents an efficient an fast synthesis procedure for an analog circuit. The proposed synthesis procedure used artificial neural network (ANN) models in combination with particle swarm optimizer. ANN has been used to develop macro-models for SPICE simulated data of analog circuit which takes transistor sizes as input and produced circuit specification as output in negligible time. The particle swarm optimizer explore the specfied design space and generates transistor sizes as potential solutions. Several synthesis results are presented which show good accuracy with respect to SPICE simulations. Since the proposed procedure does not require an SPICE simulation in the synthesis loop, it substantially reduces the design time in circuit design optimization.Item Open Access Low drop-out (LDO) voltage regulator without off-chip capacitor(Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Agarwal, Gopal; Parikh, Chetan D.Designing of Low Drop-Out Voltage Regulators (LDOs) operating without a large off-chip capacitor, having a very good transient response and maintaining the loop stability for full load current range in low supply voltage and low quiescent current environment is a challenging task. The present thesis work proposes a technique to achieve faster loop response during load transients while consuming very less quiescent current. The idea revolves around fast charging and discharging of the large equivalent capacitor at the gate of the pass transistor in response to fast load current transients. The extra circuitry added does not affect the working of main feedback loop in steady state conditions. The idea is inspired from the Nagraj’s idea of achieving high slew rate in operational amplifier which uses an auxiliary circuit to produce large currents in one of the two switching transistors, one for charging and other for discharging the slew rate limiting capacitor in the circuit. A common source amplifier (having i/p v/s o/p characteristic which closely resembles a digital inverter) followed by the large, normally off switching transistor is used here to overcome the slew rate limitation at the gate of pass transistor.Item Open Access Design of the analog front end circuit for X-ray detectors(Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Roy, Subhash Chandra; Parikh, Chetan D.The Thesis presents a novel idea to efficiently read out the value corresponding to incident X-Ray, from X-Ray sensor. A system level solution has been proposed which is unique in itself in terms of approach. A simple design of analog front end circuit for 64 channels, consisting of Charge Sensitive Preamplifier (CSP), Pulse Shaping Amplifier (PSA), Peak Detector, subtractor, Mux and ADC has been proposed. In CSP, Transmission Gate (TG) has been used, in parallel with integrating capacitor, where the NMOS is operating in weak inversion, when TG is supposed to be off. It fulfils the requirements like posing very high ac resistance, providing alternative path for DC leakage current signal, discharging integrating capacitor quickly etc. An amplifier cum level shifter has been used to match the output DC level of CSP with input DC level of PSA. PSA has been implemented as a 4th order Bessel-Butterworth low pass filter, which provides good step response, and hence output is obtained with negligible peaking. High pass filter hasn’t been used to avoid low frequency signal loss. A subtractor has been proposed after the peak detector, which is taking care of offset voltages and low frequency noise. This system till the output of shaper is providing a resolution of 1.7% against the specification of 3%.Item Open Access 1v rail to tail operational amplifier design for sample and hold circuits(Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Kumar, Mahesh; Parikh, Chetan D.At low voltage, the input common mode voltage of Operational amplifier is limited which restricts its use as a buffer. This works deals with designing a rail to rail amplifier. The Thesis presents a 1V rail to rail operational amplifier that has been used as a unity gain buffer in the sample and hold circuit for 1V 10 bit 1MSPS pipeline ADC in 0.18?m technology. The Operational amplifier is designed using dynamic level shifting technique which uses an additional input CM adapter circuit for fixing the input common mode voltage. Novelty in the input CM adapter circuit and a low value of gm fluctuation (�0.245%) has been achieved. The Operational amplifier is implemented in standard CMOS technology. An open loop architecture is chosen for the implementation of sample and hold circuit. The transmission gate switch is used in the sample and hold circuit for reducing the effect of channel charge injection and clock feedthrough. Also, the transmission gate switch offers a low resistance as compared to pMOS or nMOS switches. The sample and hold circuit speed up to 1MSPS has been achieved.Item Open Access CMOS RFIC mixer design(Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Gupta, Mukesh; Gupta, SanjeevA CMOS RF (Radio Frequency) up/down conversion mixer results in a reasonable increase in transceiver integration and a reduction in cost. The design of mixers faces many compromises between conversion gain(GC), local oscillator (LO) power, linearity, noise figure (NF), port-to-port isolation, voltage scaling and power consumption. Mixer linearity is a very important parameter in transceiver design, because system linearity is often limited by the first down-conversion mixer due to a relatively large signal compared with that at the LNA input. Since active FET (Field Effect Transistor) mixers achieve conversion gain with lower LO power than their passive counterparts, the active CMOS single-balanced and double-balanced Gilbert mixers are commonly used in the CMOS transceiver design. Compared with the single-balanced counterpart, the double balanced mixer has better port-to- port isolation due to symmetrical architecture. The double-balanced mixer has a higher noise figure due to more noise generators. The overall Gilbert mixer linearity is controlled primarily by the transconductance stage if the LO-driven transistors act as good switches. This report describes a Gilbert cell mixer with source degeneration for 900 MHz frequency. The circuit converts a 900 MHz RF signal directly to base band [IF (Intermediate frequency) 45 MHz] using an 855 MHz LO frequency. The mixer uses common source MOSFETs with inductive degeneration to convert the input RF voltage to a current. This current is then steered using a switching network composed of MOSFETs that is driven with the LO and a 180 degree phase-shifted version of the LO. Gilbert Mixer achieves gain through an active predriver [The V-I (voltage to current) converter]. This V-I converter is highly nonlinear; hence, the Gilbert Mixer distortion performance is worse. This thesis tries to propose a simple linearity improvement technique for Gilbert Cell Mixer by including an additional capacitor located in parallel with the intrinsic gate-source capacitor of the common source transconductance stage. Also, to reduce the flicker noise of the switching transistors which depends on the frequency and circuit capacitance at the common source node of the switching stage, a method is used to reduce this capacitance by adding an extra inductor that helps for simultaneously match low 1/f noise, high linearity and low NF at the expense of Conversion gain. The design is based upon the third order intermodulation distortion (IM3) and output current equations of MOSFETs and flicker noise equation when it is subjected to an ac input signal. The performance has been verified using Agilent’ Advanced Design System (ADS) simulations. The designed mixer has a voltage conversion gain of 15.804 dB, NFSSB of 6.565 dB, NFDSB=3.975 dB, IIP3 of -1.158 dBm, OIP3 USB of 14.699 dBm, OIP3 LSB of 14.646 dBm, LO to IF isolation of -27.532 dB, LO to RF isolation of -69.365 dB and RF to IF isolation of -56.554 dB for single ended RF Input.Item Open Access CMOS latched comparator design for analog to digital converters(Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Gupta, Amit Kumar; Parikh, Chetan D.Conventional comparators are at the two extremes as far as power delay product and isolation between input and output is concern. Either they achieved very good isolation at the cost of power in the preamplifier or save the static power dissipation in preamplifier in the latching mode which increases the feed through. In this thesis work we propose an optimized CMOS Latch Comparator. The simulation result based on .18um technology, shows the working of the comparator at 500 MHz, with moderate power delay product and isolation compared with the conventional architecture.Item Open Access Area reduction in 8 bit binary DAC using current multiplication(Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Upraity, Maitry; Parikh, Chetan D.A proposed current multiplication technique is applied on 8 bit binary current steering Digital-to -Analog Converters with LSB 150 μA, to reduce area. MSB 1 and MSB 2 current are first kept half to reduce area and then current multiplication is performed to get the desired output. Compare to the conventional binary current steering Digital-to-Analog Converters, 20.66% area is reduced and static errors are found within limit. Maximum Integral nonlinearity is-18μA (< LSB) and Differential nonlinearity5.02 μA (< LSB).Item Open Access Investigation of low power design of left-right leap frog array multiplier(Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Sankar, K. Ravi; Nagchoudhuri, DipankarThis thesis addresses the Low Power design of 12 bit LRLFAM at the Layout, circuit and logic levels. A new Low power Booth-Recoder (BR), and Multiplexer based partial product generated are designed using pass-Transistor logic. Several 1-Bit full adders are studied: Transmission gate, 10T, 14T, 16T, Multiplexer based and 22T. Experiments show that all these adders produce glitches when used in LRLFAM. A 22T adder is designed that best suits the LRLFA architecture. Floor planning is done with minimum interconnect length has primary aim. LRLFA architecture presented in the literature is modified to reduce the glitches and delay by adding sign extension bits in later stages than in the first row. All the layouts are done using MAGIC 7.1 for TSMC 0.25u technology. Simulations are done using L.T Spice.