M Tech Dissertations

Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3

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2007 - 20103

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Subject: search.filters.subject.Mathematical optimization

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    Ant colony optimization in routing algorithms of mobile ad hoc networks
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Agarwal, Navneet; Srivastava, Sanjay; Sunitha, V.
    The study on performance of On-demand Ant Routing Algorithm for Mobile Ad Hoc Network is done. An ant routing algorithm based on swarm intelligence and especially on Ant Colony Optimization (ACO). It describes a noval on demand Ant colony algorithm for MANETs. This algorithm tries to minimize complexity at nodes and this is achived at exoences of optimality of routing path. Inextensive set of simulation experiment, We try to set parameter of ant routing algorithms and compare Proposed algorithm with DAR,a pre existing on demand ant routing algorithms and with AODV,a reference algorithm in MANETs. The comparition base on optimal path length with respect to control overhead.
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    Particle swarm optimization based synthesis of analog circuits using neural network performance macromodels
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Saxena, Neha; Mandal, Sushanta Kumar
    This thesis presents an efficient an fast synthesis procedure for an analog circuit. The proposed synthesis procedure used artificial neural network (ANN) models in combination with particle swarm optimizer. ANN has been used to develop macro-models for SPICE simulated data of analog circuit which takes transistor sizes as input and produced circuit specification as output in negligible time. The particle swarm optimizer explore the specfied design space and generates transistor sizes as potential solutions. Several synthesis results are presented which show good accuracy with respect to SPICE simulations. Since the proposed procedure does not require an SPICE simulation in the synthesis loop, it substantially reduces the design time in circuit design optimization.
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    ASIC implementation of a pipelined bitrapezoidal architecture for discrete covariance kalman filter
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Agarwal, Vaibhav; Dubey, Rahul
    This work presents, the complete ASIC implementation of Discrete Covariance Kalman ¯lter, on a Parallel and Pipelined Bitrapezoidal Systolic Array architecture. The Kalman Filter equations are mapped on the designed architecture. This mapping requires, decomposing the overall equations, to calculate the Schur's complement, using Faddeev's algorithm. This facilitates an approach, to avoid the iterative process of calculation of matrix inverse. The designed Parallel and Pipelined architecture caters to high speed applications, by computing the single iteration of the filter in just 6 steps, each step individually taking only O(n) clock cycles. Further the processing efficiency is increased, by computing equations of O(n3) complexity in just O(n2) complexity only, where n is the order of the filter. Other unique feature of the designed architecture includes, increased robustness to rounding errors and resolving the reiterative Data input problem. The ASIC implementation was done by, Modelling the architecture using Verilog HDL,its Functional Verification was done, Logic Synthesis was done on Cadence RC 5:2 Synthesizer and Physical Synthesis on Cadence SOC Encounter. The implementation methodology presented for logic and physical synthesis resulted in efficient implementation of architecture in silicon. The design was mapped to target technology of 180nm and the synthesis results were analyzed. Physical synthesis was carried out for the same technology and the design gives final timing closure for 50MHz, which is quite high for a compute intensive algorithm like Kalman filter.