M Tech Dissertations
Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3
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Item Open Access Novel 7T SRAM cell design for low power cache applications(Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Joshi, Srawan Kumar; NagChoudhuri, DipankarScaling in integrated circuit technology directly paves way to increased package density, thereby increasing onchip power. With continuous scaling, low power design techniques results in efficient use of silicon die. Semiconductor memories are most important subsystems of modern digital systems. Modern IC’s allocate 70% of the total chip area to memory design. SRAM is used as on chip cache memory. A major part of the power consumption in any memory architecture is due to charging and discharging of highly capacitive bitlines and wordlines. Existing techniques mainly concentrated on the reduction of power due to the capacitive bitlines and wordlines. In this thesis, a new 7T SRAM cell has been proposed with a single bitline architecture which reduces the dynamic power consumption to a great extent. This proposed design resulted in power reduction of write ‘0’ and read ‘0’ operation, based on the fact that the majority of the cache writes are 0’s. A memory array of size 256Kb (512x512) was designed using the basic 6T SRAM and propsed 7T SRAM cell to carry out the simulations and compare the results for power optimization. The simulations were done using Cadence Virtuoso (ADE) tool in gpdk180 library using 0.18μm technology. With the proposed SRAM cell implementing 256Kb memory array, reduction of write power (approximately 80%) and read power (approximately 55%) is achieved compared to conventional SRAM array. There is an area overhead of 28.76% using the present 180nm technology.Item Open Access Analysis of charge injection in a MOS analog switch with impedance on source side(Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Rao, D. Srinivas; Sen, SubhajitTurning off of a transistor introduces error voltage at the output of Sample and Hold circuits which are the key components of Analog to Digital Converters (ADCs) and hence limits their accuracy of performance in high switching applications. The error voltage at output is mainly caused because of charge injection due to the carriers released from the channel and due to coupling through gate-to diffusion overlap capacitances. Hence, in order to fully understand the behaviour of charge injection in the presence of source impedance, a device is modelled and simulated in Pisces. This thesis is about modelling of an N-type Metal Oxide Semiconductor (NMOS) device in Pisces Postmini Tool with a hold capacitor on drain side, so that it can be used as a CMOS Analog switch. The main aim is to analyze the trends in output error voltage in the presence of source resistance. The output error caused due to charge injection is examined as a function of different parameters like gate voltage fall time, source resistance, input voltage, substrate concentration etc. Test structures similar to the one modelled in Pisces is simulated in 0.18μm CMOS technology for the verification purpose. It is shown that the modelled and simulated results exhibit good trend agreement.Item Open Access Design and layout of single bit per stage pipelined ADC(Dhirubhai Ambani Institute of Information and Communication Technology, 2011) Chaora, Ankeet; Sen, SubhajitThe concept of pipe-lining, often used in digital circuits, can also be applied in the analog domain. It helps to achieve higher speed where several operations must be performed serially. In this work, pipe-lining is employed to create the analog-to-digital converter. The architecture consists of N stages, each including a sample and hold circuit, an ADC, a DAC, a sub tractor and possibly an amplifier. In actual implementation we combine two or more of these functions in one circuit. By pipe-lining, in the converter an optimization can be obtained between maximum sampling clock and the speed of the circuits used. The layout of simulated pipe-lined ADC has been created and parasitic have been extracted. Rigorous pre-layout and post-layout simulations have been done and obtained results are analyzed. The single bit per stage pipe-lined ADC has been implemented in UMC 180nm technology and simulated in Cadence Virtuoso Environment.Item Open Access Capacitor mismatch in switched capacitor circuits, techniques to minimize mismatch(Dhirubhai Ambani Institute of Information and Communication Technology, 2011) Chevella, Subhash; Parikh, Chetan D.This thesis about the designing of capacitive mismatch insensitive switched capacitor amplifier for analog to digital converters (ADC). The accuracy of the conversion is an important factor. The accuracy depends upon the residue amplifier used in the designing of the pipelined ADC. So, designing of accurate gain switched capacitor (SC) amplifier is an important concern. The gain accuracy of SC amplifier depends upon the MOS switches, capacitance mismatch and operational amplifier. Among these three, the accuracy will be affected more due to the mismatch of the capacitance values. This thesis is more concentrated on capacitance mismatch. I proposed a switched capacitor amplifier whose gain is less sensitive to capacitance mismatch as compared to conventional switched capacitor amplifier. The percentage of error variation of the gain due to mismatch in proposed circuit varies from 2.1% to 2.9% but in conventional amplifier it varies from -5.1% ~ 8.5%. Proposed circuit has an improvement of 5.6%. All these simulation have done using 180nm technology in LT Spice.Item Open Access Single ended sense amplifier for DRAM(Dhirubhai Ambani Institute of Information and Communication Technology, 2011) Aggarwal, Munish; Nagchoudhuri, DipankarToday design of eDRAM is facing more challenges as the technology node is scaling down every year. Supply Voltage is also scaling down in accordance with the technology. Thus, charge on the bitlines, to sense is also decreasing, which is prominent to be affected by noise. Hierarchical based sense amplifier is used to eliminate this effect. This structure reduces the bitline capacitance to 6fF in 90nm technology node. As the ratio of the cell capacitance and the bitline capacitance is increased to 1:10 to 3.3:1 (approx.) which increased the sensing voltage to 600-750mV. Here, sense amplifier can sense the bitline without using the dummy bitlines in the structure i.e., single ended sense amplifier. It eliminates the complex bitline and dummy cell structure from the DRAM array. Cell bitline (Local Bitline LBL) is charged and discharged through the Primary Sense Amplifier (PSA) which is done by utilizing the Secondary Sense Amplifier (SSA). This Secondary Sense Amplifier is connected to the Global Bitline (GBL) through Tertiary Sense Amplifier. Activation of TSA is also not required in the refreshing cycle. Here charge transfer rate from the cell to GBL is also increased by using hierarchical based sense amplifier. Its latency of charge transfer is 1.4ns with typical overall cycle is 2ns. Present hierarchical based amplifier is also cost lower than the other hierarchical based sense amplifiers for eDRAM.Item Open Access High speed, low offset voltage cmos comparator(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Sheikh, Parveen; Parikh, Chetan D.The Analog to digital converters are the key interface blocks between the continuous time domain and the discrete-time digital domain. The performance of high-speed data conversion and digital communication interfaces is generally limited by the speed and precision with which the function of comparison can be performed. Thus, comparator speed and precision play a vital role in high performance ADC’s. CMOS comparators suitable for integration in VLSI technologies have been successfully realized for audio frequency applications, such as analog - to-digital (A/D) converters. The speed and resolution of MOSFET comparators are typically limited by the inherent MOSFET characteristics of low trans-conductance and relatively large device mismatches. However, there are several techniques for dynamic offset cancellation, dynamic biasing, and analog pipelining which significantly improve the speed and resolution achievable in an MOS based comparator. The thesis proposes a novel approach which minimizes the offset of pre-amplifier as well as the latch with increment in the speed of the comparator. The total offset thus referred back to the input is minimized and hence the pre-amplifier gain be relaxed. The CMOS circuit is implemented in 0.18 μm technology and simulated in LT-Spice.Item Open Access High-performance low-voltage current mirror design(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Gandhi, Nikunj; Parikh, Chetan D.Design of high precision analog circuits requires accounting for the mismatch between nominally identical transistors. In this work, errors affecting CMOS current mirrors due to mismatch between identical transistors are discussed, and circuit techniques to overcome these errors are studied. The dynamic current mirror (DCM) is one of the solutions to overcome mismatch problems. Dynamic current mirrors contain analog and digital components together so that errors due to process variations, temperature and ageing effect can be cancelled. Various circuit techniques such as op-amp based DCM, reduced transconductance based DCM, and cascode based DCM have been used to improve the performance of current mirrors. This thesis proposes a novel circuit for a low-voltage high-performance dynamic current mirror design. The thesis investigates the performance of analog switches at low voltages, and suggests an improved bootstrap switch; errors due to clock feed through and charge injection in the switch are analysed. A new low charge injection, voltage-boosted analog switch is recommended in the dynamic current mirror design. A bulk-driven dynamic current mirror circuit is proposed, and found to be an effective solution at low voltage. The proposed circuit is designed optimally in a 0.18µm CMOS process, in the Cadence Spectre environment. A current copying accuracy of ±0.14% is achieved under worst case conditions.Item Open Access High speed sample and hold circuit design(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Dwivedi, Varun Kumar; Parikh, Chetan D.Sampling of the time-varying input signal is the first step in any type of Analog to Digital (A/D) conversion. For Low Power and high-speed A/D converter, a high-performance Sample and Hold (S/H) circuit is needed as its front-end component. In this thesis, the high speed sample and hold circuit has been designed, requiring low power as a front end block of pipeline analog to digital converter. In this work, architectures of sample and hold circuit are studied and issues which limit the performance of sample and hold circuits are discussed. A fully differential S/H circuit using bottom plate sampling is proposed. The circuit has been designed in order to meet the specification. Amplifiers are studied and folded-cascode amplifier is chosen as an optimum architecture for switch capacitor based sample and hold circuit. The proposed circuit is designed optimally in a 180 nm CMOS process, in the Cadence Spectre environment. The speed and power achieved are 125 MSPS, 6.8mW respectively.Item Open Access Built-in self test architecture for mixed signal systems(Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Jain, Mahavir Rajmal; Mandal, Sushanta; Nagchoudhuri, DipankarBuilt-in self test architecture or BIST as we call them, are the necessity of time since the shrinking sizes of component on-chip with advance in IC technology are making it BIST artistries are being rapidly developed and used for digital circuitry due to well defied fault models and advanced designs tools and techniques available. But with more analog circuitry being built on same platform with digital circuitry, the necessity for BIST architecture of mixed signal system on chip is increasing. The proposed BIST scheme is developed to test the data converters, both DAC and ADC on chip as well as other analog IP modules depending on specification of design without/least affecting the architecture of actual design and without making use of any complex DSP circuitry. The concept of internet node access based testing of digital blocks is also used for dynamic parameter of DAC like offset voltage and gain error, monotonicity and linearity non-specific BIST scheme. Letter the digital control logic protion of SAR ADC is tested with scan-chain insertion and thus overall functionality of SRA ADC is verified. A simple comparison based method is also proposed for other type ADCs. For other anlog IPs, we propose IP-based testing where digital to analog converted test signals can be applied depending on specifications of IP design from vendor without affecting architecture of the design. The output from IPs are taken at different nodes and applied directly to ADC on chip. The digitized output response is then compared with expected response to test the functionality of the DUT and find out its deviation from desired value to achieve pre-defined level of accuracy. The design failing any of the sequence of afore-mentioned test is discarded faulty. The circuitry is designed and evaluated at schematic level using TSMC complementary metal oxide-semiconductor (CMOS) 0.5um technology.Item Open Access 6bit 800 MHz time-interleaved analog to digital converter based on successive approximation in 65 nm standard CMOS process(Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Salimath, Arunkumar; Nagchoudhuri, Dipankar; Mandal, Sushanta KumarHigh-speed analog-to-digital converters (ADCs) with resolutions of 6 bits find wide application in instrumentation, wireless systems, optical communication. This dissertation presents a 6 bit, 8 channel Time-Interleaved ADC based on Successive Approximation that performs analog processing only by means of open-loop circuits that are fully differential, thereby achieving a high conversion rate. The work involves the design of a charge redistribution hybrid-DAC, low offset comparator, shift register based phase generator and the SAR Logic. Designed in 65 nm Standard CMOS STMicroelectronics Process, across all the PVT corners, the ADC achieves SNDR of 36 dB and SFDR of 43 dBFS at 800 MHz sampling rate with low input frequencies. When the input frequency is at 300 MHz the SNDR drops to 32.6 dB. The converter draws an average power of 13.5 mW from a 1.2 V supply.