M Tech Dissertations
Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3
Browse
8 results
Search Results
Item Open Access Single electron transistor based 4-bit ALU design, simulation and optimization(Dhirubhai Ambani Institute of Information and Communication Technology, 2015) Joshi, Rathin K.; Parekh, RutuObjective of this thesis work is to create and optimize Single Electron Transistor(SET) based digital design. In present era for electronics, alternative approaches, other than CMOS (like SET,finFET,quantom dot) are much required. This is because of down scaling in MOSFET does not provide efficient results, mainly less than 10 nm feature size. In order to exhibit its applications, SET based digital design of 4-bit multifunctional ALU has been compared with 45 nm CMOS technology. Further using, circuit architecture optimization is performed, which results in significant improvement in design. Entire analysis is done in hierarchical manner: First gate level implementation and its comparison is done, followed by modular performance comparison and finally 4-bit ALU design is compared. So far, no one has done such analysis for design like SET based multifunctional computational tool. Finally, we can conclude that proposed design is energy efficient than 45 nm CMOS or hybrid SET CMOS design. In terms of PDP, SET based optimized design results in 93 % improvment than existing 45 nm CMOS. Transient analysis and PDP analysis have been done in bottom up approach. Low drivabilty and room temeprature operability were the two bottlenecks in SET based design. In this thesis work, design parameters are taken which are appropriate for room temparature, Drivability of SET in increased by modifying circuit architecture. With research advnacement, these two drawbacks have been overcome. In addition to these advantages, all the fabrication parameters are in practically feasible. Hence, proposed design can be fabricated and work at room temprature. SET’s multivalued application has also been verified by considering an example of Qunatizer. Aim behind selecting quantizer is because it is the most basic unit for SET based ADC & DAC circuits. By using only 2 SETs, quantizer is implemented, which is generally bulkier circuit in case of CMOS. This kind of ”Unlike CMOS applications” have few novel benefits with better performance.Item Open Access Low-power multi-ported register file for digital signal processors(Dhirubhai Ambani Institute of Information and Communication Technology, 2011) Aguduri, Nagamanoj Kumar; Nagchoudhuri, DipankarDigital Signal Processors (DSPs) also come under the category of processors in which Multi-ported register files can find their applications widely. Most of the DSP applications do not benefit from further speeding-up after achieving certain speed. This thesis involves in building a multi-ported register file that takes advantage of loose speed-up requirements of DSPs to reduce the power consumption. However, this can also be used in any processor which requires multiple data accesses without requiring high-end performance. A 10 read, 6 write ported 64-entry 64-bit register file is designed using combinations of techniques proposed in various earlier research works. We propose some improvements to this design in order to still lessen the power consumption. The designed Register file operates at a frequency of 250 MHz and at a power supply of 1 V. The circuits are simulated using 90nm technology. The simulation results show that this design consumes 0.00226 mW/MHz-port.Item Open Access Lifetime analysis of wireless sensor nodes using queuing models(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Anand, Guneshwar; Srivastava, SanjayProlonging the lifetime of wireless sensor networks (WSN) is one of the key issues for wireless sensor network applications. For increasing the lifetime of network, each node should conserve its energy. Sensor nodes consume different power in different operating modes. It also consumes significant amount of power while switching from one mode to another mode. So it is important that how frequently a node is changing its mode. To address this question we have used queuing theory based control policy, which finds the optimal parameter for switching between modes. We have analysed two different control policies namely, N-policy and T-policy and their effect on the lifetime of a sensor node. In N-policy, a sensor node switches its mode only when total number of packets are N. We find an optimal value of N that minimizes the energy consumption per unit time. Similarly, in T-policy whenever system becomes empty it goes on vaccation for a fixed duration T. It changes its mode only again after T unit of time and stays in the same mode as long as there is a packet. In this case also we find the optimal value of T that minimizes the energy consumption per unit time. But this improvement in lifetime comes at the cost of longer delay and larger waiting time. We have given the expression for the latency delay. Depending on the application requirement one can tune the parameters to get the best result between the energy saving and latency delay.Item Open Access Analysis and modeling of power distribution network and decoupling network design strategies for high speed digital and analog VLSI system(Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Pathak, Abhishek; Mandal, Sushanta; Nagpal, Raj Kumar; Nagchoudhuri, DipankarToday’s high speed digital and analog VLSI systems are operating in GHz frequency range. With high switching rate of the devices, power distribution network (PDN) impedance causes ripples in power supply. If PDN is not designed properly it can cause false switching, or even it can damage the device permanently. In this thesis whole power distribution network (PDN) for VLSI system has been modeled using RLC equivalent circuits which can be run on any simulation program with integrated circuit emphasis (SPICE) based simulator. Frequency dependent RLC model for printed circuit board (PCB) and package interconnects has been generated, and effects of different geometry and material of interconnects on PDN impedance profile have been analyzed. Model is compared with electromagnetic (EM) full wave simulator both for the accuracy and CPU run time and it is found that model shows good accuracy with very less CPU run time as compared to full wave simulator which can take more than a day to simulate whole geometry. To meet the target impedance of PDN, Strategies for choosing decoupling capacitors and their placement over power plane have been analyzed. Key-words: Power Integrity, power delivery network, voltage regulator, simultaneous switching noise.Item Open Access High-speed 512-point FFT single-chip processor architecture(Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Sinha, Ajay Kumar; Nagchoudhuri, Dipankar; Mandal, Sushanta KumarThis thesis present a fully parallel novel fixed point 16-bit word width 512 point FFT processor architecture. The 512 point FFT is realized by decomposing it into three 8 point FFT units. This approach reduces the number of required complex multiplication compared to the conventional radix-2 512 point FFT algorithm. It uses an ROM unit for storing the twiddle factor. The proposed architecture is designed in XILINX 8.2i using Verilog and it is functionally verified with the MATLAB. The floorplanning and timing estimation of each basic module of the proposed architecture is done based on the macro element at 0.25 CMOS technology. The core area of this chip is 99.02 mm2. The processor compute one parallel to parallel (i.e. when all input data are available in parallel and all output data are generated in parallel) 512-point FFT computation in 422 clock pulse in 4.69sec at 90 MHz operation.Item Open Access Low power SRAM design(Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Bambhaniya, Prashant; Dubey, RahulIn the past, power dissipation was not constraining factor because of device density and operating frequency was low enough. But nowadays due to increased integration and operating frequency of integrated circuits, power consumption has become an important factor. Battery operated portable devices which performing the high performance processing task also consumes lots of power. The various methodologies are used to reduce the power dissipation by optimizing the parameters that are related to power consumption of circuit. The Static RAM is used as a cache memory in the processor and also has an application in the embedded system. Due to continuous advances in the integrated circuit technology, the density of SRAMs in embedded application has grown substantially in recent years. The SRAM block is becoming indispensable block in the system-on-chips (SoCs). The larger density SRAM block has a highly capacitive bit lines and data lines. The dynamic power of SRAM is mainly due to charging and discharging of highly capacitive lines. To perform the write operation in the SRAM cell to flip the data value, nearly full voltage swings is required on the bit line. This full voltage swing on the highly capacitive bit lines will consumes a greater amount power according to law of CV2f. Thus voltage swing reduction is an effective way to decrease the power dissipation. The current mode sensing technique is proposed to give the small voltage swing on the bit lines during write operation. In the proposed method the layout and simulation is done for the one bit line pair for three different methodologies. The bit line interference of selected cell with adjacent selected and non selected cell is also checked out. The proposed current conveyor method has shown an improvement in terms power dissipation over the voltage write and current read (VWCR) and current write and current read (CWCR) method without comprising the performance.Item Open Access Design methodology for architecting application specific instruction set processor(Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Desai, Meghana; Dubey, RahulApplication Specific Instruction-set Processors (ASIP), also referred as extensible processors, represent the state-of-the-art microprocessor architecture. ASIPs are practically leading towards the realization of System-on-a-Chip (SoC) concept; as processor, customised for an application, can be easily integrated in a SoC as pre-designed and pre-verified soft RTL block. Most significant and challenging part for these flexible or programmable processors is the design methodology. The challenge lies in providing a simple configurable design space such that the outcome is optimised, efficient and customised application specific processor hardware, with very short design cycle time. The bottle neck for a processor is chiefly the data path design, as it has computational intensive functional units which add to the major portion of hardware area along with timing. In case of ASIP as well, data path modification is to be achieved as per the requirements. Current electronic design automation (EDA) tools are intelligent and if exploited well can actually help in providing various optimizations in the design. The implemented design approach is based on these aspects of selection of accurate data path elements along with distributed control path and exploiting the inbuilt functionality of EDA tools for generating user defined architecture. In this project a non-pipelined as well as five stage pipelined processor fabrics are implemented with configurable parameters. A library of basic arithmetic functional units is created from which a component of desired characteristic is selected and integrated in the data path. Synthesis of modified processor core is performed with a set of constraints to achieve required trade off between area, power and timing. Multi-supply voltage feature of the synthesis tool is exploited to meet the timing closure of the generated processor core.Item Open Access Low power microprocessor design(Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Bhatt, Vishal; Dubey, RahulThis research work tries to reduce the power consumption of a processor with signal processing features. For low power design, focus is on developing ‘Low power synthesizable Register File’, as the initial study shows that there is potential for significant benefit by doing this. Two techniques are proposed and implemented in this work, (1) Compiler Driven Register Access (CDRA) (2) Register Windowing. Here, Register Windowing is an extension to an earlier technique called ‘Register Isolation’. Benchmarks used for evaluating design in terms of power consumption and performance, simulate conditions encountered by the processor in control and DSP applications. After applying various low power techniques, average power reduction obtained across benchmarks is 1.5% and the maximum power reduction obtained is 2.6% when compared to Base Processor which is a customized version of MIPS architecture with signal processing capability.