M Tech Dissertations

Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3

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Subject: search.filters.subject.Oscillators

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Now showing 1 - 5 of 5
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    10-bit high speed high SFDR current steering DAC
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Bapodra, Dhairya B.; Parikh, Chetan D.
    The Thesis presents an attempt to design a 10-bit High Speed High SFDR Current Steering DAC with a simple and different approach. Most of earlier approaches contain complex design and bulky unary portion. Here an approach tried that uses sub-segmentation of unary part. By using sub-segmentation of unary part, reduction in complex decoder block can be introduced. The issue of synchronization is tackle by a latch that is previously proposed for tackling very high frequency. Here by segmentation of unary part area as well as complexity is reduced for decoder. And the sentence that is always true “Simpler Designs are faster”. And reduction in complexity leads to reduction in error sources.
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    Design of low-voltage, low-power, wide-band CMOS LC VCO using active inductors
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Sesha Sai, Aduru Venkata Raghava; Parikh, Chetan D.
    In this thesis the design of low-voltage, low-power, wide-band CMOS LC VCO using active inductor has been proposed. The oscillator is based upon the classic LC-tuned negative-resistance topology, with a novel active inductor using a low-voltage gyrator topology with a feedback resistance, where feedback resistance is realized by a NMOS operating in triode region whose bias voltage tunes the inductance of the active inductor and hence the frequency of VCO. The simulation results shows that this VCO operates in a 1.19 GHz to 2.49 GHz , while consuming 1.09 mW from a 1.2V power supply. The VCO’s phase noise level is -86.9 dBc/Hz at 1 MHz offset from a 1.55 GHz carrier. The deviation of the phase noise is 11.5 dBc/Hz during this tuning range. All the circuit simulations of VCO were simulated in SpectreRF using TSMC 0.18μm CMOS technology.
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    Design of CMOS voltage controlled oscillator for high tuning range
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Nayudu, Bharath Kumar; Gupta, Sanjeev
    The main objective of the work is to design a CMOS voltage controlled oscillator for higher tuning range. Today there is a great need for multi-standard wireless receivers in the wireless communications. A receiver is to be designed such that it receives data from the different frequency bands and standards. It is essential to design an oscillator to adhere to some of the standards like CDMA, GSM, GPRS and others. CMOS was the ideal choice for this work because of its low power consumption compared to other technologies and its immunity to the noise. In the design of the tank circuit, binary weighted capacitive array technique (BWCA), discrete variable inductor by using MOS switch and variable capacitor for continuous tuning have been used. By using all the above three techniques, a higher tuning range has been achieved.
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    Fault diagnosis algorithm for a flash ADC using oscillation based testing technique
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Aggarwal, Divya; Parikh, Chetan D.
    With the advent of system-on-a-chip (SoC) designs, the semiconductor industry wants to solve problems that constrain the coexistence of analog and digital cores on a single chip. The complexities of modern (SoC's), comprising of analog, digital and even Radio-Frequency (RF) blocks on a single chip, are surpassing all the previous limits. Merging so many different technologies poses new challenges, such as developing design and test methodologies capable of ensuring system performance and reliability for a reasonable design effort. Digital testing has developed in to a complete science in the last forty years, but analog and mixed-signal are still in its initial state. The lack of standard models and methodologies is worsening this situation. This work addresses the problem of fault coverage in analog and mixed signal circuits and proposes a fault diagnosis algorithm using Oscillation based Testing Technique. Present calibration techniques compensate for deviations in the measured parameters and do not correct the faulty value, because the faulty value cannot be obtained. A fault diagnosis technique able to perform fault identification (obtain fault values) will lay the groundwork for the development of more effective calibration techniques. Analog to digital converter (ADC) is used as a test vehicle to demonstrate the capability of the proposed OBIST technique. This technique employ Oscillation frequency test data for fault location and identification of the analog components in the converter. In the flash ADC, a fault causes deviation of Oscillation frequency from the ideal one. Hence, it can be considered as a functional signature of the ADC and this property is employed for fault diagnosis. ADC's are virtually in all modern SoC's and hence are one of the most important modules in analog and mixed-signal designs. Here, we have 3-bit, 1 GHz CMOS Flash ADC, designed in 0.18 μm CMOS technology as a benchmark. The simulation results prove that this technique shows an excellent coverage of catastrophic as well as a good coverage of parametric faults, also the algorithm proposed locate the faults in resistive ladder and comparators. The area overhead is very less in this techniques and it works on the circuit speed so, lesser test time.
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    Novel local oscillator circuit for sub-harmonic mixer
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2005) Kishore, G. Pavan Krishna; Biswas, R. N.; Parikh, Chetan D.
    Direct Conversion RF transceiver is the enabling technique for the next generation cellular and personal communication devices striving for miniaturization, long life of battery and cost effectiveness. Existing techniques of Direct Conversion suffer from undesired carrier radiation from the receiver. This leads to distortion in the signal received by the users in the close proximity. The proposed transceiver design is an approach to address the discussed issue of carrier radiation. The existing systems use Sub Harmonic mixer to overcome this problem with a sinusoidal Local Oscillator (LO) running at half of the required carrier frequency. The W-CDMA systems which use QPSK modulation need eight phases of the LO, the generation of which consume large power due to the linear circuits used. The proposed design implements the octet phase LO using non-linear circuits. This leads to the significant improvement in terms of power consumption and area. The core work of the thesis involves designing and analysis of new circuit topology that uses CMOS inverter chain for generating the octet-phase trapezoidal LO, to drive the Sub Harmonic mixer. The improvements are possible through the reduced size of transistors used in inverter and its non-linear operation. Thorough analysis of the circuit is performed for both sinusoidal and trapezoidal LO. Competitive results are obtained from the analysis of the design in terms of conversion gain, carrier suppression and Input referred 3rd order Intercept Point (IIP3). The design is modified to make it robust for varying ambient temperatures using a junction diode. A two port model of the Sub Harmonic mixer is derived, which proves a non-sinusoidal LO can be used in place of sinusoidal.