Design of Low Power Time-to-Digital Converter in 0.18?m CMOS

dc.accession.number	T00665
dc.classification.ddc	621.39814 AGR
dc.contributor.advisor	Mishra, Biswajit
dc.contributor.author	Agrawal, Jatin
dc.date.accessioned	2018-05-17T09:29:58Z
dc.date.accessioned	2025-06-28T10:25:43Z
dc.date.available	2018-05-17T09:29:58Z
dc.date.issued	2017
dc.degree	M.Tech.
dc.description.abstract	A full custom, all-digital, low power Time-to-Digital Converter (TDC) based on a Time-based Analog to Digital Converter (TAD) is presented. The proposed architecture contains a 20-bit ripple counter, 16-bit latch, an encoder, an edge detector and a Ring Delay Line (RDL) with appropriate control logic circuit. The TDC-IC core has an area of 0.026mm2 in 0.18?m CMOS that achieves resolution of 586.4ps/LSB and 201.8ps/LSB, power consumption of 32.5?W and 315.5?W, with the distance calculation up to 2949.4km and 1015.7km at 1V and 1.8V respectively,making it feasible for distance measurement in space applications.
dc.identifier.citation	Jatin Agrawal(2017).Design of Low Power Time-to-Digital Converter in 0.18?m CMOS.Dhirubhai Ambani Institute of Information and Communication Technology.ix, 45 p.(Acc.No: T00665)
dc.identifier.uri	http://drsr.daiict.ac.in/handle/123456789/699
dc.publisher	Dhirubhai Ambani Institute of Information and Communication Technology
dc.student.id	201511012
dc.subject	FPGA Implementation
dc.subject	Resolution Improvement Technique
dc.subject	Ring Delay Line
dc.title	Design of Low Power Time-to-Digital Converter in 0.18?m CMOS
dc.type	Dissertation

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