CMOS current-based mixed-signal architecture for vector-matrix multiplication
dc.accession.number | T00345 | |
dc.classification.ddc | 621.39732 CHH | |
dc.contributor.advisor | Zaveri, Mazad S | |
dc.contributor.author | Chhaya, Vaibhav | |
dc.date.accessioned | 2017-06-10T14:39:40Z | |
dc.date.accessioned | 2025-06-28T10:20:44Z | |
dc.date.available | 2017-06-10T14:39:40Z | |
dc.date.issued | 2012 | |
dc.degree | M. Tech | |
dc.description.abstract | In present days electronic devices become faster. Computations like vector matrix multiplication become more and more compliant and lengthy. For that CMOS based vectormatrix multiplication architecture, with external digital interface and internal current-based analog operation is presented here. The basic circuits within this architecture are: a binary multiplier that contains a static memory, a current source, a current accumulator and current-to-voltage convertor. The external operand arrives sequentially, so a serial-to-parallel shift-register memory is also implemented. In LTSpice, using 180nm CMOS technology, I have implemented a vector-matrix multiplier circuit that simultaneously performs 64×4 binary multiplications. | |
dc.identifier.citation | Chhaya, Vaibhav (2012). CMOS current-based mixed-signal architecture for vector-matrix multiplication. Dhirubhai Ambani Institute of Information and Communication Technology, 40 p. (Acc.No: T00345) | |
dc.identifier.uri | http://drsr.daiict.ac.in/handle/123456789/382 | |
dc.publisher | Dhirubhai Ambani Institute of Information and Communication Technology | |
dc.student.id | 201011009 | |
dc.subject | CMOS | |
dc.subject | LTSpice | |
dc.subject | Vectormatrix multiplication architecture | |
dc.title | CMOS current-based mixed-signal architecture for vector-matrix multiplication | |
dc.type | Dissertation |
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