ASIC implementation of a pipelined bitrapezoidal architecture for discrete covariance kalman filter

dc.accession.numberT00127
dc.classification.ddc629.831222 AGA
dc.contributor.advisorDubey, Rahul
dc.contributor.authorAgarwal, Vaibhav
dc.date.accessioned2017-06-10T14:37:14Z
dc.date.accessioned2025-06-28T10:19:13Z
dc.date.available2017-06-10T14:37:14Z
dc.date.issued2007
dc.degreeM. Tech
dc.description.abstractThis work presents, the complete ASIC implementation of Discrete Covariance Kalman ¯lter, on a Parallel and Pipelined Bitrapezoidal Systolic Array architecture. The Kalman Filter equations are mapped on the designed architecture. This mapping requires, decomposing the overall equations, to calculate the Schur's complement, using Faddeev's algorithm. This facilitates an approach, to avoid the iterative process of calculation of matrix inverse. The designed Parallel and Pipelined architecture caters to high speed applications, by computing the single iteration of the filter in just 6 steps, each step individually taking only O(n) clock cycles. Further the processing efficiency is increased, by computing equations of O(n3) complexity in just O(n2) complexity only, where n is the order of the filter. Other unique feature of the designed architecture includes, increased robustness to rounding errors and resolving the reiterative Data input problem. The ASIC implementation was done by, Modelling the architecture using Verilog HDL,its Functional Verification was done, Logic Synthesis was done on Cadence RC 5:2 Synthesizer and Physical Synthesis on Cadence SOC Encounter. The implementation methodology presented for logic and physical synthesis resulted in efficient implementation of architecture in silicon. The design was mapped to target technology of 180nm and the synthesis results were analyzed. Physical synthesis was carried out for the same technology and the design gives final timing closure for 50MHz, which is quite high for a compute intensive algorithm like Kalman filter.
dc.identifier.citationAgarwal, Vaibhav (2007). ASIC implementation of a pipelined bitrapezoidal architecture for discrete covariance kalman filter. Dhirubhai Ambani Institute of Information and Communication Technology, ix, 44 p. (Acc.No: T00127)
dc.identifier.urihttp://drsr.daiict.ac.in/handle/123456789/164
dc.publisherDhirubhai Ambani Institute of Information and Communication Technology
dc.student.id200511037
dc.subjectKalman filtering
dc.subjectNonlinear systems
dc.subjectMathematical optimization
dc.subjectAdaptive filters
dc.subjectFilters digital electronic
dc.subjectASIC
dc.titleASIC implementation of a pipelined bitrapezoidal architecture for discrete covariance kalman filter
dc.typeDissertation

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