6bit 800 MHz time-interleaved analog to digital converter based on successive approximation in 65 nm standard CMOS process

dc.accession.numberT00205
dc.classification.ddc621.38159 SAL
dc.contributor.advisorNagchoudhuri, Dipankar
dc.contributor.advisorMandal, Sushanta Kumar
dc.contributor.authorSalimath, Arunkumar
dc.date.accessioned2017-06-10T14:37:49Z
dc.date.accessioned2025-06-28T10:19:38Z
dc.date.available2017-06-10T14:37:49Z
dc.date.issued2009
dc.degreeM. Tech
dc.description.abstractHigh-speed analog-to-digital converters (ADCs) with resolutions of 6 bits find wide application in instrumentation, wireless systems, optical communication. This dissertation presents a 6 bit, 8 channel Time-Interleaved ADC based on Successive Approximation that performs analog processing only by means of open-loop circuits that are fully differential, thereby achieving a high conversion rate. The work involves the design of a charge redistribution hybrid-DAC, low offset comparator, shift register based phase generator and the SAR Logic. Designed in 65 nm Standard CMOS STMicroelectronics Process, across all the PVT corners, the ADC achieves SNDR of 36 dB and SFDR of 43 dBFS at 800 MHz sampling rate with low input frequencies. When the input frequency is at 300 MHz the SNDR drops to 32.6 dB. The converter draws an average power of 13.5 mW from a 1.2 V supply.
dc.identifier.citationSalimath, Arunkumar (2009). 6bit 800 MHz time-interleaved analog to digital converter based on successive approximation in 65 nm standard CMOS process. Dhirubhai Ambani Institute of Information and Communication Technology, vii, 55 p. (Acc.No: T00205)
dc.identifier.urihttp://drsr.daiict.ac.in/handle/123456789/242
dc.publisherDhirubhai Ambani Institute of Information and Communication Technology
dc.student.id200711012
dc.subjectComputer simulation
dc.subjectAnalog-to-digital converters
dc.subjectMetal oxide semiconductors
dc.subjectAnalog-to-digital converters
dc.subjectCatalogs
dc.title6bit 800 MHz time-interleaved analog to digital converter based on successive approximation in 65 nm standard CMOS process
dc.typeDissertation

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