Design of low power and high speed decoder for 1MB memory

dc.accession.numberT00156
dc.classification.ddc621.395 GUP
dc.contributor.advisorNagchoudhuri, Dipankar
dc.contributor.authorGupta, Punam Sen
dc.date.accessioned2017-06-10T14:37:25Z
dc.date.accessioned2025-06-28T10:19:19Z
dc.date.available2017-06-10T14:37:25Z
dc.date.issued2008
dc.degreeM. Tech
dc.description.abstractTechnology scaling is accompanied by rise in leakage power dissipation. This thesis proposes a voltage controllable circuit in the feedback path of the decoder, which drastically reduces the standby leakage current with minimum loss in speed and slightly overheads in terms of chip area. This circuit generates slightly lower supply voltage when the load circuitry is in the standby mode thereby raises the Vt of the CMOS transistors and hence reduces leakage power dissipation The overall power dissipation of a 7x128 decoder is reduced from 0.928mW to 0.584mW for 1Mb Memory with voltage controllable circuit, namely 37% lowering in power dissipation. The operating voltage for the design is 1.2 V. Layout is done in magic 7.1 version in 180nm technology. The simulations are done in LT spice.
dc.identifier.citationGupta, Punam Sen (2008). Design of low power and high speed decoder for 1MB memory. Dhirubhai Ambani Institute of Information and Communication Technology, vii, 43 p. (Acc.No: T00156)
dc.identifier.urihttp://drsr.daiict.ac.in/handle/123456789/193
dc.publisherDhirubhai Ambani Institute of Information and Communication Technology
dc.student.id200611017
dc.subjectElectronic circuit design
dc.subjectCoding theory
dc.subjectDecoders
dc.subjectElectronics
dc.subjectCoding
dc.subjectComputer programs
dc.subjectLarge scale integration
dc.subjectLinear integrated circuits - Design and construction
dc.subjectMemory
dc.subjectSemiconductor devices
dc.subjectVery large scale integration
dc.titleDesign of low power and high speed decoder for 1MB memory
dc.typeDissertation

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