Low power microprocessor design

dc.accession.numberT00115
dc.classification.ddc621.3916 BHA
dc.contributor.advisorDubey, Rahul
dc.contributor.authorBhatt, Vishal
dc.date.accessioned2017-06-10T14:37:10Z
dc.date.accessioned2025-06-28T10:19:11Z
dc.date.available2017-06-10T14:37:10Z
dc.date.issued2007
dc.degreeM. Tech
dc.description.abstractThis research work tries to reduce the power consumption of a processor with signal processing features. For low power design, focus is on developing ‘Low power synthesizable Register File’, as the initial study shows that there is potential for significant benefit by doing this. Two techniques are proposed and implemented in this work, (1) Compiler Driven Register Access (CDRA) (2) Register Windowing. Here, Register Windowing is an extension to an earlier technique called ‘Register Isolation’. Benchmarks used for evaluating design in terms of power consumption and performance, simulate conditions encountered by the processor in control and DSP applications. After applying various low power techniques, average power reduction obtained across benchmarks is 1.5% and the maximum power reduction obtained is 2.6% when compared to Base Processor which is a customized version of MIPS architecture with signal processing capability.
dc.identifier.citationBhatt, Vishal (2007). Low power microprocessor design. Dhirubhai Ambani Institute of Information and Communication Technology, x, 79 p. (Acc.No: T00115)
dc.identifier.urihttp://drsr.daiict.ac.in/handle/123456789/152
dc.publisherDhirubhai Ambani Institute of Information and Communication Technology
dc.student.id200511016
dc.subjectMicroprocessors
dc.subjectEnergy conservation
dc.subjectLow voltage integrated circuits
dc.subjectDesign and construction
dc.subjectComputer architecture
dc.titleLow power microprocessor design
dc.typeDissertation

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