10-bit high speed high SFDR current steering DAC

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dc.accession.numberT00204
dc.classification.ddc621.39814 BAP
dc.contributor.advisorParikh, Chetan D.
dc.contributor.authorBapodra, Dhairya B.
dc.date.accessioned2017-06-10T14:37:48Z
dc.date.accessioned2025-06-28T10:19:47Z
dc.date.available2017-06-10T14:37:48Z
dc.date.issued2009
dc.degreeM. Tech
dc.description.abstractThe Thesis presents an attempt to design a 10-bit High Speed High SFDR Current Steering DAC with a simple and different approach. Most of earlier approaches contain complex design and bulky unary portion. Here an approach tried that uses sub-segmentation of unary part. By using sub-segmentation of unary part, reduction in complex decoder block can be introduced. The issue of synchronization is tackle by a latch that is previously proposed for tackling very high frequency. Here by segmentation of unary part area as well as complexity is reduced for decoder. And the sentence that is always true “Simpler Designs are faster”. And reduction in complexity leads to reduction in error sources.
dc.identifier.citationBapodra, Dhairya B. (2009). 10-bit high speed high SFDR current steering DAC. Dhirubhai Ambani Institute of Information and Communication Technology, ix, 38 p. (Acc.No: T00204)
dc.identifier.urihttp://drsr.daiict.ac.in/handle/123456789/241
dc.publisherDhirubhai Ambani Institute of Information and Communication Technology
dc.student.id200711011
dc.subjectDigital-to-analog converters
dc.subjectDesign and construction
dc.subjectElectronic circuit design
dc.subjectOscillators
dc.title10-bit high speed high SFDR current steering DAC
dc.typeDissertation

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