Low Power ASIC Implementation of SC-FDMA

Abstract

"Single Carrier-Frequency Division Multiple Access (SC-FDMA), a modified version of Orthogonal Frequency Division Multiple Access (OFDMA) is the preferred uplink access scheme for Long Term Evolution (LTE). We aim to design a Low Power Application Specific Integrated Circuit (ASIC) of SC-FDMA transmitter which would eventually support longer battery life in smart-phones. The digital implementation is done using Verilog which is a Hardware Description Language (HDL). The Thesis shows implementation of two designs: Design 1 (8-point DFT with 64-point IFFT) and Design 2 (32/16-point DFT with 256/128-point IFFT). Design 2 supports the concept of Hardware Reconfigurability depending upon the channel gain. Both designs have been pipelined in order to meet the timing requirements ensuring no violations occur. Proposed power reduction techniques are clock gating for dynamic power reduction and addition of Frank Constant Amplitude Zero Auto-Correlation (CAZAC) sequences [16] for Peak-to-Average (PAPR) minimization. After the implementation of the above mentioned techniques, the front-end analysis is done using Cadence Encounter RTL Compiler tool. Nangate 45nm Open Cell Slow Library is chosen for synthesis."