Image Compression using 2D-Discrete Wavelet Transform on a Reconfigurable Architecture

Abstract

"This thesis presents a hardware implementation of 2D-DWT, an image compression technique, on a reconfigurable architecture targeting image processing applications developed in-house as the part of the Ph.D. research work. The architecture is already capable of performing various other digital signal and image processing functions such as CORDIC, FIR filtering, 2D convolution and DCT etc. . In this thesis, we present the mapping of a configurable 2D-DWT algorithm using convolution method with separable filter approach having filter length up to 8 taps on the reconfigurable architecture with results verified on hardware. The hardware platform used is Xilinx University Program Virtex II Pro (XUPV2P) FPGA development board. The frequency of operation is 37.26 MHz and the number of clock cycles required is 496 per 8 8 block of the N N image with total clock cycles equal to 31/4 N2 for 1 level of decomposition and the compression achieved is 75%. The compression can be further increased by computing higher levels of decomposition of 2D-DWT."