Browsing by Author "Vyas, Pavan R."

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    • HDL based implementation of a node of hierarchical temporal memory. 

      Vyas, Pavan R. (Dhirubhai Ambani Institute of Information and Communication Technology, 2013)
      The main intention of this thesis is to give the basic information about the implementation of a node of one of the neural network algorithms. The main purpose of this thesis is to design, implement and analyze the node ...