Browsing by Subject "Floor plan"
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Physical design implementation of “ARP Block-4” module at 28nm “CHIPTOP” module at 90nm
(Dhirubhai Ambani Institute of Information and Communication Technology, 2019)VLSI design flow from RTL to GDSII consists of two phases, namely front-end design and back-end design. The physical design is the process of transforming a circuit description into the physical layout, which describes the ...