Now showing items 1-20 of 20

    • 6bit 800 MHz time-interleaved analog to digital converter based on successive approximation in 65 nm standard CMOS process 

      Salimath, Arunkumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
      High-speed analog-to-digital converters (ADCs) with resolutions of 6 bits find wide application in instrumentation, wireless systems, optical communication. This dissertation presents a 6 bit, 8 channel Time-Interleaved ...
    • Adaptive biased switched capacitor filters 

      Bajaj, Garima (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      The demand from today’s handheld devices, such as laptop, ipod, cellphones is to have a long battery life with no compromises in speed. The devices dissipate power even in standby mode also. Op-amp is a major block in all ...
    • Analysis of charge injection in a MOS analog switch with impedance on source side 

      Rao, D. Srinivas (Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
      Turning off of a transistor introduces error voltage at the output of Sample and Hold circuits which are the key components of Analog to Digital Converters (ADCs) and hence limits their accuracy of performance in high ...
    • Built-in self test architecture for mixed signal systems 

      Jain, Mahavir Rajmal (Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
      Built-in self test architecture or BIST as we call them, are the necessity of time since the shrinking sizes of component on-chip with advance in IC technology are making it BIST artistries are being rapidly developed and ...
    • Capacitor mismatch in switched capacitor circuits, techniques to minimize mismatch 

      Chevella, Subhash (Dhirubhai Ambani Institute of Information and Communication Technology, 2011)
      This thesis about the designing of capacitive mismatch insensitive switched capacitor amplifier for analog to digital converters (ADC). The accuracy of the conversion is an important factor. The accuracy depends upon the ...
    • Design and layout of single bit per stage pipelined ADC 

      Chaora, Ankeet (Dhirubhai Ambani Institute of Information and Communication Technology, 2011)
      The concept of pipe-lining, often used in digital circuits, can also be applied in the analog domain. It helps to achieve higher speed where several operations must be performed serially. In this work, pipe-lining is ...
    • Design of a CMOS variable gain amplifier 

      Verma, Vivek (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      In advanced CMOS technologies as device dimensions are decreasing, requirement for lower supply voltages are increasing to make certain device reliability. So, challenges for analog circuit designers are to discover new ...
    • Design of a high speed I/O buffer 

      Rathore, Akhil (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      In high speed serial transmission of data, output buffer creates the bottleneck. Current Mode Logic (CML) buffers have gained wide acceptance in most high speed serial interfaces as they reach speed of the order of Gbp/s. ...
    • Design of a low power high slew rate OPAMP and to study its impact on sigma delta modulator's performance 

      Verma, Aseem (Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
      This thesis presents the work done on the design of a low-power, high slew rate opamp and subsequently the design of a fully-differential second order Switched-Capacitor architecture of a Sigma Delta modulator in 1.8 V, ...
    • Design of CMOS voltage controlled oscillator for high tuning range 

      Nayudu, Bharath Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
      The main objective of the work is to design a CMOS voltage controlled oscillator for higher tuning range. Today there is a great need for multi-standard wireless receivers in the wireless communications. A receiver is to ...
    • Design of low voltage high performance voltage controlled oscillator 

      Ramesh, R (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      In this thesis an ultra low voltage differential capacitive feedback VCO is being proposed .The VCO operates at very low supply voltage of 0.6V.The VCO uses techniques like Forward Body Bias (FBB), and capacitive feedback ...
    • Design of voltage reference circuits 

      Panchal, Bhavi (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      Shrinking device dimensions in advancing CMOS technologies require lower supply voltages to ensure device reliability. As a result, analog circuit designers are faced with many challenges in finding new ways to build analog ...
    • High speed sample and hold circuit design 

      Dwivedi, Varun Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
      Sampling of the time-varying input signal is the first step in any type of Analog to Digital (A/D) conversion. For Low Power and high-speed A/D converter, a high-performance Sample and Hold (S/H) circuit is needed as its ...
    • High speed, low offset voltage cmos comparator 

      Sheikh, Parveen (Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
      The Analog to digital converters are the key interface blocks between the continuous time domain and the discrete-time digital domain. The performance of high-speed data conversion and digital communication interfaces is ...
    • High-performance low-voltage current mirror design 

      Gandhi, Nikunj (Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
      Design of high precision analog circuits requires accounting for the mismatch between nominally identical transistors. In this work, errors affecting CMOS current mirrors due to mismatch between identical transistors are ...
    • Implementation of constant gm CMOS op-amp input stage using overlapping of transition region at 0.18 um technology 

      Singh, Ram Sahay (Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
      Operational amplifier is the backbone of most of analog circuit design. For low voltage applications, op-amp should have a rail-to-rail common mode input voltage. This report describes the implementation of a constant gm ...
    • Low power high slew-rate adaptive biasing circuit for CMOS amplifiers 

      Rao, A. Narayana (Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
      Adaptive biasing technique in analog and mixed signal integrated circuit design is used mainly to reduce the power and improve the driving capability. It has found many applications, like power amplifiers in RF communication ...
    • Novel 7T SRAM cell design for low power cache applications 

      Joshi, Srawan Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
      Scaling in integrated circuit technology directly paves way to increased package density, thereby increasing onchip power. With continuous scaling, low power design techniques results in efficient use of silicon die. ...
    • Single ended sense amplifier for DRAM 

      Aggarwal, Munish (Dhirubhai Ambani Institute of Information and Communication Technology, 2011)
      Today design of eDRAM is facing more challenges as the technology node is scaling down every year. Supply Voltage is also scaling down in accordance with the technology. Thus, charge on the bitlines, to sense is also ...
    • Tool to calculate the width and length of capacitor for switched-capacitor band pass filter 

      Doshi, Kaushal J. (Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
      The switched capacitor (SC) circuits find their applications in many fields. Due to their lower size at low frequencies, higher density can be achieved compared to active RC counterparts. Still there are nonlinerarities ...