Now showing items 1-3 of 3

    • Area reduction in 8 bit binary DAC using current multiplication 

      Upraity, Maitry (Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
      A proposed current multiplication technique is applied on 8 bit binary current steering Digital-to -Analog Converters with LSB 150 μA, to reduce area. MSB 1 and MSB 2 current are first kept half to reduce area and then ...
    • CMOS latched comparator design for analog to digital converters 

      Gupta, Amit Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
      Conventional comparators are at the two extremes as far as power delay product and isolation between input and output is concern. Either they achieved very good isolation at the cost of power in the preamplifier or save ...
    • CMOS RFIC mixer design 

      Gupta, Mukesh (Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
      A CMOS RF (Radio Frequency) up/down conversion mixer results in a reasonable increase in transceiver integration and a reduction in cost. The design of mixers faces many compromises between conversion gain(GC), local ...