Browsing by Subject "VLSI"

Now showing items 1-6 of 6

    • Built-in self-test for a flash analog to digital converter 

      Bhalerao, Mangesh (Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
      The intricacies of modern System on Chips (SoCs), comprising of analog, digital and even Redio-Frequency (RF) blocks on a single chip, are surpassing all previous conceivable limits. A more perplexing problem now is not ...

    • Design of frequency synthesizable delay locked loop 

      Shah, Hardik K. (Dhirubhai Ambani Institute of Information and Communication Technology, 2004)
      As the speed performance of VLSI systems increases rapidly, more emphasis is placed on suppressing skew and jitter in the clocks. Phase-locked loops (PLLs) and delay-locked loops (DLLs) have been typically employed in ...

    • Efficient scan-based BIST scheme for low heat dissipation and reduced test application time 

      Shah, Malav (Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
      Switching activity during test application can be significantly higher than that during normal circuit operation in many circuits. This is due to the fact that the correlation between consecutive test vectors is significantly ...

    • Low power BIST architecture for fast multiplier embedded core 

      Vij, Aditya (Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
      A typical core is deeply embedded in the chip of a system so that direct access to its input/output is not possible. Built in self test (BIST) structures are excellent solutions for testing embedded cores. In this work, ...

    • Low power improved full scan BIST 

      Parashar, Umesh (Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
      Low power testing of VLSI circuits has recently become an area of concern due to yield and reliability problems. Past research on low power testing has shown that, switching activity and test time are the main factors that ...

    • Statistical delay modeling and analysis for system on chip 

      Patel, Jay (Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
      It is seen that designing using conventional methodologies in Deep Sub Micron geometries, at times, ends up in very pessimistic design and less yield. This is because, today’s tools don’t consider statistical variation of ...