Low power improved full scan BIST
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Low power testing of VLSI circuits has recently become an area of concern due to yield and reliability problems. Past research on low power testing has shown that, switching activity and test time are the main factors that influence the heat dissipation during test. This thesis presents a scan-based BIST scheme that reduces switching activity (SA) in the circuit under test (CUT) and test application time without compromising in fault coverage (FC). The proposed BIST scheme is based on combined BIST approach (combining both test-per-scan and test-per-clock test methodologies), two different functional lengths during scan, and a low transition random test pattern generator (LT-RTPG) as TPG. It takes optimal advantage of three techniques and reaches desired FC faster with a significant reduction in switching activity. Experiments conducted on different ISCAS’89 benchmark circuits report up to 24% reduction in SA and up to 80% reduction in the test length. The register transfer level (RTL) implementation of the proposed BIST is done on a 4-bit sequential multiplier circuit (for 90nm technology; Spartan-3 FPGA) to validate effectiveness of the proposed BIST under constraints of supply voltage, glitches, and technology parameters (for 90nm). Experimental results show that proposed BIST achieves 13.75% reduction in the average power dissipation compared to LFSR based BIST.
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