Linearity enhancement technique for low noise amplifiers
Purohit, Amit Gopal M.
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The development of CMOS technology in to deep sub micron enables the use of such technology for implementation for GHz RF circuits. Personal communication needs a low cost and low noise RF transceiver for cellular applications using CMOS technology. Low Noise amplifier is one of the basic building blocks in any receiver system. The LNA determines the overall system’s noise performance, as it is first gain block after antenna. LNA must amplify the input signal with lowest noise possible because it decides the whole device’s performance under noisy signal. In order to have high receiver sensitivity the LNA is required to have not only low noise figure but also high gain and low input VSWR. <p/> <p/>Normally, LNA design involves the tradeoff between noise figure, gain, linearity and power consumption. Consequently, the goal of LNA design is to meet system requirements with minimum noise figure and highest possible linearity. This thesis attempts to propose a linearity enhancing technique to simultaneously match high linearity and low noise figure requirements. The design is based upon the third order intermodulation product (IM3) and output current equations of MOSFET when it is subjected to an ac input signal. By using these expressions, the design principle and advantages for the mentioned LNA technique are explained. <p/>In this thesis a linearity enhancement technique is proposed which increases third order intermodulation product of low noise amplifier (IIP3) up to +10 dBm without a large increase in overall noise figure. Input impedance of low noise amplifier is matched to 50Ω while output impedance is kept high and unmatched. Prelayout simulation results, layout and postlayout simulation results are given to show that the technique really works satisfactory and gives good linearity.
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