• Login
    JavaScript is disabled for your browser. Some features of this site may not work without it.

    Browse

    All of DSpaceCommunities & CollectionsBy Issue DateAuthorsTitlesSubjectsThis CollectionBy Issue DateAuthorsTitlesSubjects

    My Account

    LoginRegister

    Statistics

    View Usage StatisticsView Google Analytics Statistics

    A 0.18µ low power dual-mode transceiver front-end design for high speed bluetooth systems

    Thumbnail
    View/Open
    200411038.pdf (1.485Mb)
    Date
    2006
    Author
    Dalwadi, Gaurav
    Metadata
    Show full item record
    Abstract
    Today’s market trend is to possess a single multi-purpose, multi-functional personal device for various wireless personal area network (WPAN) applications. So it raises a great demand to develop multi-mode/multi-standard transceiver compatible to all these applications, which is a challengeable task. Moreover, today’s multi-media technology requires enhancement in speed performance. With respect to Bluetooth Standard, even version 1.2 with 1 Mbps data rate or version 2.0 + EDR with 2 or 3 Mbps data rate are not adequate considering current requirements. Bluetooth SIG has also specified another correlated standard called physical draft specifications with 4, 8 or 12 Mbps data rate to solve this issue. Currently, there are no transceivers available in the market that provides compatibility among all these versions. The core work of the thesis involves designing and analysis the multi-standard transceiver front-end system that gives compatibility with all three versions, solving RF design issues such like image rejection, flicker noise, DC offset etc. by using dual-conversion technique with choosing proper local oscillator frequency architecture. Furthermore, as Bluetooth is widely used in portable communication devices, its transceiver design requires miniaturization, long life of battery and cost-effectiveness. This thesis reports the transceiver analog front-end part designed with 0.18µ CMOS technology and 1.8 V supply. The improvement in power consumption has been obtained by implementing some recently developed low power designs of low noise amplifier, power amplifier, variable gain amplifier and limiter matching with the specifications derived through system design. Overall system and circuit-designs give very low system noise figure and hence, receiver sensitivity up to -92 dBm has been successfully achieved.
    URI
    http://drsr.daiict.ac.in/handle/123456789/136
    Collections
    • M Tech Dissertations [923]

    Resource Centre copyright © 2006-2017 
    Contact Us | Send Feedback
    Theme by 
    Atmire NV
     

     


    Resource Centre copyright © 2006-2017 
    Contact Us | Send Feedback
    Theme by 
    Atmire NV