Architecture design for preliminary ECG analysis system using new DFT based analysis technique
This thesis proposes a hardware architecture of an ASIC for a portable ECG analysis system. The device is meant to record and analyze ECG signals in real time so as to detect the presence of abnormalities. In order to achieve this, a totally new approach for the analysis of ECG signals using Discrete Fourier Transform (DFT) is developed as a part of the thesis. An important finding of the project, through experiments performed on real ECG data in MATLAB, is that the phases of first 8 DFT coefficients of beat-wise ECG signals give distinguishing patterns for normal and abnormal beats. With this idea of variable size DFT as the basis, a much simplified form of the technique with fixed 32 point DFT is derived without significantly disturbing the patterns so as to make it suitable for hardware implementation. The translation of the algorithm to hardware architecture has been done in a way so as to achieve optimization in terms of area as well as power by minimizing the number of computations. One of the important features of the proposed architecture is the synchronization of the complete system which processes an asynchronous signal, i.e. the ECG beats, in real time. The thesis gives the custom Register Transfer Level architecture for the processing block of the system, which is meant for selecting fixed number of samples from every beat and do a customized DFT phase computation for detecting abnormalities. The project proposes a very simple technique for the beat detection as a part of optimization. Since the incoming signal is much slower than the processing rate, the proposed architecture is designed with the flexibility of adding extra functionalities in the system other than ECG analysis which if possible can use the same processing hardware during the wait periods.
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