Designing of an efficient power clock generation circuit for complementary pass-transistor adiabatic logic carry save multiplier

Abstract

This thesis presents a novel four-phase power clock generator for low power adiabatic logic without using inductors. The power clock generator is designed using current mirror arrangement of PMOS and NMOS transistors. Different logic families have been studied and Complementary Pass-transistor Adiabatic Logic (CPAL) is chosen to implement an adiabatic carry save multiplier as it gives less energy dissipation per cycle than other logic families at higher load capacitances and higher loads. The power clock is designed for CPAL which requires four phase trapezoidal waveform. An 8-bit carry save multiplier is designed which is used as load to clock generation circuit. The clock generator consumes equal energy per cycle at all frequencies. The control logic required for clock generation circuit is also simple to implement. Conversion efficiency of the order of 10% is obtained for an equivalent load capacitance of 2pF. The simulations are done using LT spice in 0.25μm TSMC technology. Layouts are drawn in MAGIC 7.1.