FPGA implementation of image compression algorithm using wavelet transform
This work presents FPGA implementation of image compression algorithm by using wavelet transform. Here the emphasis has been made on algorithmic encoding, the first step of image compression problem. The transform that has been used for algorithmic encoding is the „Discrete Wavelet transform‟. The Wavelet family which has been used for this purpose is the „Haar Wavelet family. Various issues involved in hardware implementation of Wavelet Transform such as fractional interpretation, signed Q-format, range of gray scale values, memory requirement and addressing schemes have been discussed. A functional unit has been proposed which calculates the Wavelet transform of input pixel values. An efficient use of „Block RAM‟ present in FPGA has been proposed by placing the initial pixel values and then placing the computed Wavelet transform values back in this memory itself. A suitable way to tackle the issue of storing intermediate wavelet transform values by using a buffer memory has been suggested. This removes the need of having an external memory and thus the time required in accessing this memory reduces drastically. A special emphasis in order to use this memory in accordance with the requirement of image processing algorithms has been made by deriving the necessary addressing schemes. This is done in order to have the correct placement of transformed values in memory. Here we have used the Dual port feature of the Block RAM with one port providing multiple pixel values to the functional unit and other being used to write transformed values one at a time. Along with this, the DCM available in FPGA has been used to address issue of skew and „set up time‟ involved with the clocks in digital design. A delayed version of system clock is sent to memory so that all addresses and enable signals calculated with reference to system clock are stable when active edge of clock is received by memory. All these modules are incorporated in a top module which provides the Wavelet transform of an image. The modelling of the architecture has been done by using Verilog Hardware Description Language and the functional simulation has been done by using Xilinx ISE Simulator. The synthesis of the design has been done by using Xilinx Synthesis Tool (XST) of Xilinx. The total amount of the resources being utilized is reported and it comes out well within reach of Spartan 3E FPGA, our target device. The maximum clock frequency which can be used for the design comes out to be 23 MHz which is quite high for a compute intensive algorithm like Discrete Wavelet Transform.
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