Self-calibrating technique for digital-to-analog converter in successive approximation register analog-to-digital converter
Successive Approximation Register (SAR) analog to digital converter resolution is limited mainly by the capacitor ratio error; comparator offset voltage and capacitor voltage dependence error. A SAR ADC resolution is limited to 10-bit due above errors. Resolution can be increased by using calibration techniques for these errors. From the calibration of capacitor ratio error and comparator offset voltage 16-bit resolution can be achieved. Calibration of capacitor voltage dependence error is necessary for resolution more than 16-bit. This thesis proposes the self calibration technique for capacitor ratio error in differential SAR analog to digital converter. Using this calibration technique capacitor ratio error is minimized. Linear voltage coefficient of capacitor is canceled by the differential SAR ADC but, comparator has limitation of finite common mode rejection ratio (CMRR). In this work self calibration of capacitor voltage dependence error is also discussed in detail.
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