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CMOS current-based mixed-signal architecture for vector-matrix multiplication
(Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
In present days electronic devices become faster. Computations like vector matrix
multiplication become more and more compliant and lengthy. For that CMOS based vectormatrix
multiplication architecture, with external ...
Design of a novel high linearity down conversion mixer for GSM band applications
(Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
Double balanced Gilbert cell mixer (GCM) is the mostly used kind of mixer as it provides
conversion gain and has port to port isolation. This mixer lacks in linearity and noise figure
which are to be taken care in designing ...
All-digital delay-line based ultra wide band transmitter architecture in 0.18m CMOS
(Dhirubhai Ambani Institute of Information and Communication Technology, 2014)
Ultra-Wide Band (UWB) technology has recently become a viable option for commercial wireless applications that require high data-rate and ultra low power demand. UWB technology operates between the frequency range of 3.1 ...
Design of 64-bit SRAM using single electron transistor
(Dhirubhai Ambani Institute of Information and Communication Technology, 2016)
The present day devices demand memory chips with larger size and smallphysical dimensions. This drives the designer to design high density memorydevices. The memory designed using CMOS technology do not have comparablespeed ...
Design and Analysis of Energy Neutral Wireless Sensor Nodes for Health and Environmental Monitoring Applications
(Dhirubhai Ambani Institute of Information and Communication Technology, 2016)
This thesis demonstrates investigation of an Energy Neutral System using EnergyHarvesters for Wireless Sensor Nodes (WSNs). For this purpose, we have implementedan Energy Harvesting system which consists of three parts: ...
Auto tuning circuit for continuous time filters
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
This thesis presents the design of auto tuning circuit for continuous time filters and is designed for applications that require high linearity and moderate precision. This scheme is used to improve tuning range of 50% and ...
Physical design implementation of “ARP Block-4” module at 28nm “CHIPTOP” module at 90nm
(Dhirubhai Ambani Institute of Information and Communication Technology, 2019)
VLSI design flow from RTL to GDSII consists of two phases, namely front-end design and back-end design. The physical design is the process of transforming a circuit description into the physical layout, which describes the ...