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Architecture design for preliminary ECG analysis system using new DFT based analysis technique
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
This thesis proposes a hardware architecture of an ASIC for a portable ECG analysis system. The device is meant to record and analyze ECG signals in real time so as to detect the presence of abnormalities. In order to ...
High-speed 512-point FFT single-chip processor architecture
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
This thesis present a fully parallel novel fixed point 16-bit word width 512 point FFT processor architecture. The 512 point FFT is realized by decomposing it into three 8 point FFT units. This approach reduces the number ...