Search
Now showing items 1-6 of 6
Statistical co-analysis, robust optimization and diagnosis of USB 2.0 system for signal and power integrity
(Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
Signal Integrity (SI) and Power Integrity (PI) are the most critical issues as semiconductor industry is moving towards higher operational speeds. Signal integrity and power integrity are such issues that should be looked ...
Design of low-voltage, low-power, wide-band CMOS LC VCO using active inductors
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
In this thesis the design of low-voltage, low-power, wide-band CMOS LC VCO using active inductor has been proposed. The oscillator is based upon the classic LC-tuned negative-resistance topology, with a novel active inductor ...
Built-in self test architecture for mixed signal systems
(Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
Built-in self test architecture or BIST as we call them, are the necessity of time since the shrinking sizes of component on-chip with advance in IC technology are making it BIST artistries are being rapidly developed and ...
Effect of channel asymmetry on reputation based cooperation mechanisms in mobile ad-hoc networks
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
Enforced cooperation among MANET nodes is an active research issue. In applications, where the users have different goals and there is no central authority to control them, users may become selfish. These nodes may not ...
Multirate signal processing in digital communications
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
Fundamentals of multirate signal processing and perfect reconstruction filter banks are revisited. An attempt is made to develop a good understanding of concepts by connecting the filter bank design issues to the concepts ...
High-speed 512-point FFT single-chip processor architecture
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
This thesis present a fully parallel novel fixed point 16-bit word width 512 point FFT processor architecture. The 512 point FFT is realized by decomposing it into three 8 point FFT units. This approach reduces the number ...