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Design of low-voltage, low-power, wide-band CMOS LC VCO using active inductors
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
In this thesis the design of low-voltage, low-power, wide-band CMOS LC VCO using active inductor has been proposed. The oscillator is based upon the classic LC-tuned negative-resistance topology, with a novel active inductor ...
Analysis and modeling of power distribution network and decoupling network design strategies for high speed digital and analog VLSI system
(Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
Today’s high speed digital and analog VLSI systems are operating in GHz frequency range. With high switching rate of the devices, power distribution network (PDN) impedance causes ripples in power supply. If PDN is not ...
Built-in self test architecture for mixed signal systems
(Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
Built-in self test architecture or BIST as we call them, are the necessity of time since the shrinking sizes of component on-chip with advance in IC technology are making it BIST artistries are being rapidly developed and ...
Design of a CMOS variable gain amplifier
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
In advanced CMOS technologies as device dimensions are decreasing, requirement for lower supply voltages are increasing to make certain device reliability. So, challenges for analog circuit designers are to discover new ...
Low power SRAM design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
In the past, power dissipation was not constraining factor because of device density and operating frequency was low enough. But nowadays due to increased integration and operating frequency of integrated circuits, power ...
Efficient scan-based BIST scheme for low heat dissipation and reduced test application time
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
Switching activity during test application can be significantly higher than that during normal circuit operation in many circuits. This is due to the fact that the correlation between consecutive test vectors is significantly ...
Designing of an efficient power clock generation circuit for complementary pass-transistor adiabatic logic carry save multiplier
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
This thesis presents a novel four-phase power clock generator for low power adiabatic logic without using inductors. The power clock generator is designed using current mirror arrangement of PMOS and NMOS transistors. ...