Search
Now showing items 1-10 of 38
FM based pipeline ADC
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
This thesis aims at designing a new architecture for an FM based pipelined Analog to Digital Converter (ADC). It is based on the fact that power is a function of voltage and therefore handling with voltage becomes a difficult ...
Extremely low voltage operational amplifier design with rail-to-rail input common mode range
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
Increasing trends towards battery operated systems demand circuits to be designed at low voltages. Low voltage operation severely limits the operational amplifier as a voltage buffer as the input common mode range available ...
Implementation of constant gm CMOS op-amp input stage using overlapping of transition region at 0.18 um technology
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
Operational amplifier is the backbone of most of analog circuit design. For low voltage applications, op-amp should have a rail-to-rail common mode input voltage. This report describes the implementation of a constant gm ...
Speech driven facial animation system
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
This thesis is concerned with the problem of synthesizing animating face driven by new audio sequence, which is not present in the previously recorded database. The main focus of the thesis is on exploring the efficient ...
Resource discovery in computational grids: quantitative comparison and analysis of MDS and DHT
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
Grid Information Services provided by most of the grid middlewares aim at discovering resources in wake of large number of Grid nodes. Many Grid Information Services (GIS) have been deployed in different Grid middlewares. ...
Low power and high speed sample and hold circuit
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
In this thesis work the design of a high speed and low power CMOS sample and hold circuit as a front-end block of pipelined analog-to-digital converter is described. The circuit consists of bottom-plate sampling with ...
Secure and efficient key assignment scheme for dynamic access control in a hierarchy
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
The users belonging to an organization are often assigned different access permissions depending on their security class. In this situation, the users belonging to a higher security class are allowed access to the information ...
Mobility aware MANET routing protocol using cross layer design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
Mobile Adhoc Network (MANET) is a dynamic network with time varying topology and time varying network resources. Due to the error-prone wireless channel and high mobility, traditional protocols of wired networks cannot be ...
Statistical delay modeling and analysis for system on chip
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
It is seen that designing using conventional methodologies in Deep Sub Micron geometries, at times, ends up in very pessimistic design and less yield. This is because, today’s tools don’t consider statistical variation of ...
Design of a low power, high speed MAC unit
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
MAC operation is the main computational kernel in any digital signal processing architectures. MAC consumes nearly 2/3 portion of total power dissipated in a DSP block. This thesis deals with the design of a low power, ...