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Now showing items 11-20 of 20
Design of a high speed I/O buffer
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
In high speed serial transmission of data, output buffer creates the bottleneck. Current Mode Logic (CML) buffers have gained wide acceptance in most high speed serial interfaces as they reach speed of the order of Gbp/s. ...
Design of voltage reference circuits
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
Shrinking device dimensions in advancing CMOS technologies require lower supply voltages to ensure device reliability. As a result, analog circuit designers are faced with many challenges in finding new ways to build analog ...
High speed, low offset voltage cmos comparator
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
The Analog to digital converters are the key interface blocks between the continuous time domain and the discrete-time digital domain. The performance of high-speed data conversion and digital communication interfaces is ...
High speed sample and hold circuit design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
Sampling of the time-varying input signal is the first step in any type of Analog to Digital (A/D) conversion. For Low Power and high-speed A/D converter, a high-performance Sample and Hold (S/H) circuit is needed as its ...
High-performance low-voltage current mirror design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
Design of high precision analog circuits requires accounting for the mismatch between nominally identical transistors. In this work, errors affecting CMOS current mirrors due to mismatch between identical transistors are ...
Novel 7T SRAM cell design for low power cache applications
(Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
Scaling in integrated circuit technology directly paves way to increased package density,
thereby increasing onchip power. With continuous scaling, low power design techniques
results in efficient use of silicon die. ...
Single ended sense amplifier for DRAM
(Dhirubhai Ambani Institute of Information and Communication Technology, 2011)
Today design of eDRAM is facing more challenges as the technology node is scaling
down every year. Supply Voltage is also scaling down in accordance with the technology. Thus, charge on the bitlines, to sense is also ...
Tool to calculate the width and length of capacitor for switched-capacitor band pass filter
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
The switched capacitor (SC) circuits find their applications in many fields. Due to their lower size at low frequencies, higher density can be achieved compared to active RC counterparts. Still there are nonlinerarities ...
Design of low voltage high performance voltage controlled oscillator
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
In this thesis an ultra low voltage differential capacitive feedback VCO is being proposed .The VCO operates at very low supply voltage of 0.6V.The VCO uses techniques like Forward Body Bias (FBB), and capacitive feedback ...
6bit 800 MHz time-interleaved analog to digital converter based on successive approximation in 65 nm standard CMOS process
(Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
High-speed analog-to-digital converters (ADCs) with resolutions of 6 bits find wide application in instrumentation, wireless systems, optical communication. This dissertation presents a 6 bit, 8 channel Time-Interleaved ...