Design & layout of a low voltage folding & interpolation ADC for high speed applications

Abstract

Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC) plays a vital role in mixed analog signalling, communication and digital signal processing world. Now a day, the demand for designing of high speed, low power and low voltage ADCs are increasing tremendously in high speed data processing applications. In the folding and interpolation ADCs folding amplifiers have the serious bandwidth limitation problem because of larger parasitic capacitance and resistance at the output node. In this thesis work a low voltage and high speed folding and interpolation ADC is implemented using current steering CMOS folding amplifier followed by transresistance amplifier (TRA) in UMC 180nm CMOS technology. The current steering folding amplifier significantly reduces power as well as number of tail current sources compared to the conventional folding amplifier. Transresistance amplifier, which is connected at the output of folding amplifier, avoids the analog bandwidth limitation problem. MSB and LSB bits are generated simultaneously at the output therefore sample and hold circuit is not required in this architecture. This proposed circuit works at 1.8V power supply and 85 MSamples/S and consumes 70mW power. Simulation and Layout of Folding and Interpolation ADC were done using UMC CMOS 180nm technology in the Cadence Analog Design Environment