| dc.contributor.advisor | Zaveri, Mazad S | |
| dc.contributor.author | Kacheria, Rachit M. | |
| dc.date.accessioned | 2017-06-10T14:40:26Z | |
| dc.date.available | 2017-06-10T14:40:26Z | |
| dc.date.issued | 2013 | |
| dc.identifier.citation | Kacheria, Rachit M. (2013). HDL implementation of palm associative memory. Dhirubhai Ambani Institute of Information and Communication Technology, viii, 34 p. (Acc.No: T00389) | |
| dc.identifier.uri | http://drsr.daiict.ac.in/handle/123456789/426 | |
| dc.description.abstract | The objective of this paper is to implement and analyze the palm associative memory proposed by G. Palm [1]. In this paper, a design implementation of this algorithm, based on Verilog HDL (hardware description language) and MATLAB programming language is proposed. Xilinx Spartan-3e FPGA (Field Programming Gate Array) is required for simulation purpose, which performs arithmetic operations for implementing associative memory. The simulation results will be obtained with Xilinx ISE 10.1 and MATLAB R2010a. The results are analyzed in terms of operating frequency and chip utilization. It also summarizes the Time of Computation and Hardware for Logic implementation for different input vector size in the system. | |
| dc.publisher | Dhirubhai Ambani Institute of Information and Communication Technology | |
| dc.subject | Hardware Description Languages | |
| dc.subject | HDL | |
| dc.subject | HDL Implementation | |
| dc.subject | palm associative memory | |
| dc.subject | Computer Hardware Description Languages | |
| dc.classification.ddc | 621.392 KAC | |
| dc.title | HDL implementation of palm associative memory | |
| dc.type | Dissertation | |
| dc.degree | M. Tech | |
| dc.student.id | 201111010 | |
| dc.accession.number | T00389 | |
