Phase locked loop (PLL) charge pump (CP) design for low power communication applications
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Phase Locked Loop (PLL) plays a vital role in electronic applications, microprocessors, communication & computers. Recent advancement in wireless technologies & CMOS technologies show many advantages for medical diagnostic & treatment. Now a day, wireless implantable medical devices use RF trans-receiver to exchange data between body & external base station, need low power, low noise Phase Locked Loop (PLL). In this thesis, a Phase Locked Loop (PLL) Synthesizer & charge pump are implemented using BSIM3 180nm CMOS technology which will useful in low power communication applications like Medical Implant Communication Service (MICS) band devices. PLL is control system generating an output signal & its phase is related to an input reference signal phase. PLL Synthesizer can generate range of frequencies from fix input frequency. It consists of Phase Frequency Detector (PFD), Charge Pump (CP), Low Pass Filter (LPF), Voltage Controlled Oscillator (VCO) & Divider. PFD compares the input & output frequency phase & its difference go into CP. CP generate current proportional to phase difference & give it to LPF. LPF generate control voltage & give it to VCO. VCO generate output frequency proportional to control voltage. The output frequency goes into divider in feedback loop & divider output goes to PFD. This whole PLL Synthesizer is implemented using BSIM3 180nm CMOS technology in LTspice-IV tool & simulate in it. I have also implemented Modified CP which will useful for low power PLL Synthesizer. This PLL Synthesizer circuit works at 1.8V power supply, spur of -55dB & consume 3.2mW power. Proposed Modified CP has almost same up-down current & very low leakage current of 1.97pA but in the design random jitter or phase noise has not been considered.
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