Verification of address generation unit and register file of digital signal processor using system verilog

Abstract

Verification of the digital systems become important part in the industry. In this thesis I verified two modules of ASIP DSP processor using System Verilog. The Thesis describes the design of Address Generation Unit (AGU) and Register File (RF) of Application Specific Instruction Set DSP and it is separated in two parts. Some theoretical background, description of the different steps for the designing of AGU and its verification plan has been shown in first part of the thesis - in chapter 2 and in chapter 3. Here AGU is designed for generating address for convolution process where circular addressing mode is used.

The second part contains Register File theoretical background and its general designing steps, its simulation result and its verification plan in System Verilog. Both AGU and RF which are the DUTs in this thesis, have been implemented in Verilog, and their simulation and verification done in ModelSim® software.