Dynamic recognfiguration of cache memories for leakage power reduction
Kalidindi, Vijaya Rama Raju
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Power is increasingly becoming a design constraint for low power VLSI circuits. It has become one of the most important paradigms of design convergence for future icroprocessors. The scaling of the CMOS channel length to below 65 nm not only increased the chip density to the ULSI range but also placed power dissipation on an equal footing with performance as a figure of merit in digital circuit design. This increase in power dissipation raised the curtains for advanced cooling technologies. There are many advanced techniques to reduce dynamic and static power. In today’s microprocessors cache memories occupy considerable amount of area and consume huge amounts of power. Huge on-chip caches might be beneficial in terms of storage capacity but take up a lot of area and also dissipate about 30% of the total power. In a huge cache, if an application uses a small part of the cache, then the idle portion contributes to leakage power/energy. If this idle portion could be switched off, vast amounts of power could be saved. This thesis aims to reduce the leakage power by "reconfiguring" the cache according to the application’s needs without affecting the performance of the processor. Methods, which change the size and associativity dynamically, have been implemented and analyzed.
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