Power aware software design parallel programming with DVFS
In the first decade of the 21st century, one of the fastest growing areas is Mobile Internet Devices (MIDs). This segment requires devices to be effecient in terms of power usage. Getting maximum performance in the limited power budget available with such devices is now the topmost goal. This led to muti-core systems gaining prominence due to their lower power consumption compared to their single core counterparts. To gain advantage of these systems, parallel programming is a must. When using multi-core systems, having the ability to change the performance in the form of frequency of each core according to the program running on the core will result in higher power savings. This is provided by the DVFS (Dynamic Frequency and Voltage Scaling) subsystem. The Operating system controls the DVFS subsystem independent of the program running on the core and dependent only on the utilisation of the core resulting in high latencies, which when reduced can save power. This dissertation aims to investigate the ARM architecture, which is an inherently low power and widely used in MIDs, for energy efficient High Performance Computing. For doing so, a Beowulf Cluster was created with Single Board Computers (SBCs) sporting the Qualcomm Snapdragon 800, an ARM Cortex A-15 based processor. In addition, a DVFS library was created which allows a programmer to manipulate the DVFS subsystem to achieve higher energy efficiency. A combination of Parallel programming in conjunction with user-controlled DVFS has been proposed and evaluated as a novel powersaving technique.
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