Single precision floating point matrix multiplier using low power arithmetic circuits
The main objective of this thesis work is to implement a Single Precision Floating Point Matrix Multiplier with the help of basic low power arithmetic circuits. Such circuit can be used in various digital signal processing, such as Image and Speech processing. Matrix Multiplier is made up of various sub-blocks which include selection of column and row value through multiplexer, partial product calculation through multiplier and cumulative addition of partial product terms through adder. All the circuits are implemented on Cadence environment – Virtuoso. The technology node used for the implementation is 180nm and the library used is UMC180. Comparison of the different architectures is done on the basis of various parameters such as power, delay and energy-delay product (EDP). As architecture plays an important role in reducing power, basic logic blocks which dissipate least power are considered. Comparisons between different architectures of the same function are done on the basis of parameters mentioned above. As major concern in most circuits is power dissipated over a particular time, so the energy-delay product is an important parameter to characterize the circuits. The circuits are simulated for varying voltages and comparison is done at supply voltages at 1.8V and 1V (above threshold).
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