Design of 16-bit 1MSamples/s differential SAR analog to digital converter
This work focusses on design of 16-bit, 1MSamples/s differential SAR ADC converter.We have applied split ADC architecture to SAR converter. The design canbe broadly classified in two parts viz. design of ideal A/D converter using VerilogAand design and simulation of non ideal A/D converter using Matlab. Allthe design parameters are taken according to 180nm process. The ideal VerilogAmodel serves as template for developing non ideal A/D converter. This workinvolves development of self calibrating error correction algorithm for capacitormismatches and the system noise. The whole system is simulated behaviourallyusing Matlab and tested for the performance metrics like INL and DNL. The selfcalibrating error correction algorithm shows significant improvement in speed ofconvergence and the accuracy. Even after introducing 10 times more than typicalcapacitor mismatches, it could successfully draw the INL and DNL within 0.5LSB and shows significant improvement in frequency responce.
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