Show simple item record

dc.contributor.advisorMishra, Biswajit
dc.contributor.authorAgrawal, Jatin
dc.date.accessioned2018-05-17T09:29:58Z
dc.date.available2018-05-17T09:29:58Z
dc.date.issued2017
dc.identifier.citationJatin Agrawal(2017).Design of Low Power Time-to-Digital Converter in 0.18?m CMOS.Dhirubhai Ambani Institute of Information and Communication Technology.ix, 45 p.(Acc.No: T00665)
dc.identifier.urihttp://drsr.daiict.ac.in//handle/123456789/699
dc.description.abstractA full custom, all-digital, low power Time-to-Digital Converter (TDC) based on a Time-based Analog to Digital Converter (TAD) is presented. The proposed architecture contains a 20-bit ripple counter, 16-bit latch, an encoder, an edge detector and a Ring Delay Line (RDL) with appropriate control logic circuit. The TDC-IC core has an area of 0.026mm2 in 0.18?m CMOS that achieves resolution of 586.4ps/LSB and 201.8ps/LSB, power consumption of 32.5?W and 315.5?W, with the distance calculation up to 2949.4km and 1015.7km at 1V and 1.8V respectively,making it feasible for distance measurement in space applications.
dc.publisherDhirubhai Ambani Institute of Information and Communication Technology
dc.subjectFPGA Implementation
dc.subjectResolution Improvement Technique
dc.subjectRing Delay Line
dc.classification.ddc621.39814 AGR
dc.titleDesign of Low Power Time-to-Digital Converter in 0.18?m CMOS
dc.typeDissertation
dc.degreeM.Tech.
dc.student.id201511012
dc.accession.numberT00665


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record